Optimizing High-Level Synthesis Designs with Retrieval-Augmented Large Language Models
On the map: Retrieval-augmented generation → RAG for code
Abstract (arXiv)
High-level synthesis (HLS) allows hardware designers to create hardware designs with high-level programming languages like C/C++/OpenCL, which greatly improves hardware design productivity. However, existing HLS flows require programmers' hardware design expertise and rely on programmers' manual code transformations and directive annotations to guide compiler optimizations. Optimizing HLS designs requires non-trivial HLS expertise and tedious iterative process in HLS code optimization. Automating HLS code optimizations has become a burning need. Recently, large language models (LLMs) trained on massive code and programming tasks have demonstrated remarkable proficiency in comprehending code, showing the ability to handle domain-specific programming queries directly without labor-intensive fine-tuning. In this work, we propose a novel retrieval-augmented LLM-based approach to effectively optimize high-level synthesis (HLS) programs. Our proposed method leverages few-shot learning, enabling large language models to adopt domain-specific knowledge through natural language prompts. We propose a unique framework, Retrieve Augmented Large Language Model Aided Design (RALAD), designed to enhance LLMs' performance in HLS code optimization tasks. RALAD employs advanced embedding techniques and top-k search algorithms to dynamically source relevant knowledge from extensive databases, thereby providing contextually appropriate responses to complex programming queries. Our implementation of RALAD on two specialized domains, utilizing comparatively smaller language models, achieves an impressive 80% success rate in compilation tasks and outperforms general LLMs by 3.7 -- 19× in latency improvement.
Key facts. Cited by 6 papers in the map (data through 7 Oct 2026). Placed in RAG for code, one of 15 directions in Retrieval-augmented generation. Builds on 7 of its 14 references that are in the map. First posted on arXiv 9 Oct 2024.
Builds on
7 of 14 references.
References · 7
- 2020Retrieval-Augmented Generation for Knowledge-Intensive NLP Taskscited by 9,160
- 2021CodeT5: Identifier-aware Unified Pre-trained Encoder-Decoder Models for Code Understanding and Generationcited by 890
- 2023A Comprehensive Overview of Large Language Modelscited by 639
- 2022DocPrompting: Generating Code by Retrieving the Docscited by 151
- 2023GPT4AIGChip: Towards Next-Generation AI Accelerator Design Automation via Large Language Modelscited by 59
- 2021A Replication Study of Dense Passage Retrievercited by 37
- 2018Parallel Programming for FPGAscited by 9
Built on by
Citing papers per year: 2025: 4; 2026: 2.
6 papers.
- 2025LLM-DSE: Searching Accelerator Parameters with LLM Agentscited by 7
- 2025iDSE: Navigating Design Space Exploration in High-Level Synthesis Using LLMscited by 6
- 2026Bench4HLS: End-to-End Evaluation of LLMs in High-Level Synthesis Code Generationcited by 2
- 2025Iceberg: Enhancing HLS Modeling with Synthetic Datacited by 1
- 2025Advancing AI-assisted Hardware Design with Hierarchical Decentralized Training and Personalized Inference-Time Optimizationcited by 0
- 2026HLSmith: An Expert-Guided Agentic Framework for C/C++-to-HLS Translationcited by 0
- 2026HLSmith: An Expert-Guided Agentic Framework for C/C++-to-HLS Translation7 Aug 2026
- 2026Bench4HLS: End-to-End Evaluation of LLMs in High-Level Synthesis Code Generation16 Jan 2026
- 2025Iceberg: Enhancing HLS Modeling with Synthetic Data14 Jul 2025
- 2025iDSE: Navigating Design Space Exploration in High-Level Synthesis Using LLMs28 May 2025
- 2025LLM-DSE: Searching Accelerator Parameters with LLM Agents18 May 2025
- 2025Advancing AI-assisted Hardware Design with Hierarchical Decentralized Training and Personalized Inference-Time Optimization21 Apr 2025
Similar, not cited
Close in wording, no citation either way
- 2025SAGE-HLS: Syntax-Aware AST-Guided LLM for High-Level Synthesis Code Generation
- 2023Large Language Models for Compiler Optimization
- 2025Exploring Code Language Models for Automated HLS-based Hardware Generation: Benchmark, Infrastructure and Analysis
- 2025TimelyHLS: LLM-Based Timing-Aware and Architecture-Specific FPGA HLS Optimization
- 2025HDLCoRe: A Training-Free Framework for Mitigating Hallucinations in LLM-Generated HDL
- 2026From Brute Force to Semantic Insight: Performance-Guided Data Transformation Design with LLMs
- 2024Automated C/C++ Program Repair for High-Level Synthesis via Large Language Models
- 2026RAG-Enhanced Kernel-Based Heuristic Synthesis (RKHS): A Structured Methodology Using Large Language Models for Hardware Design ↗