mlsanityData to 7 Oct 2026

CktEvo: Repository-Level RTL Code Benchmark for Design Evolution

arXiv 2603.08718 ↗First posted 10 Feb 2026cs.AR cs.AIcited by 3

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Abstract (arXiv)

Register-Transfer Level (RTL) coding is an iterative, repository-scale process in which Power, Performance, and Area (PPA) emerge from interactions across many files and the downstream toolchain. While large language models (LLMs) have recently been applied to hardware design, most efforts focus on generation or debugging from natural-language prompts, where ambiguity and hallucinations necessitate expert review. A separate line of work begins from formal inputs, yet typically optimizes high-level synthesis or isolated modules and remains decoupled from cross-file dependencies. In this work, we present CktEvo, a benchmark and reference framework for repo-level RTL evolution. Unlike prior benchmarks consisting of isolated snippets, our benchmark targets complete IP cores where PPA emerges from cross-file dependencies. Our benchmark packages several high-quality Verilog repositories from real-world designs. We formalize the task as: given an initial repository, produce edits that preserve functional behavior while improving PPA. We also provide a closed-loop framework that couples LLM-proposed edits with toolchain feedback to enable cross-file modifications and iterative repair at repository scale. Our experiments demonstrate that the reference framework realizes PPA improvements without any human interactions. CktEvo establishes a rigorous and executable foundation for studying LLM-assisted RTL optimization that matters for engineering practice: repository-level, function-preserving, and PPA-driven.

Key facts. Cited by 3 papers in the map (data through 7 Oct 2026). Builds on 25 of its 34 references that are in the map. First posted on arXiv 10 Feb 2026.

Builds on

25 of 34 references.

References · 25

  1. 2023Qwen Technical Reportcited by 3,273
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  5. 2024RepairAgent: An Autonomous, LLM-Based Agent for Program Repaircited by 225
  6. 2023VeriGen: A Large Language Model for Verilog Code Generationcited by 197
  7. 2023RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Modelcited by 143
  8. 2023Keep the Conversation Going: Fixing 162 out of 337 bugs for 0.42 each using ChatGPTcited by 125
  9. 2024OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflectioncited by 56
  10. 2024Towards LLM-Powered Verilog RTL Assistant: Self-Verification and Self-Correctioncited by 39
  11. 2025A Survey of Research in Large Language Models for Electronic Design Automationcited by 38
  12. 2024A Systematic Literature Review on Large Language Models for Automated Program Repaircited by 37
13 more
  1. 2024MEIC: Re-thinking RTL Debug Automation using LLMscited by 25
  2. 2025ScaleRTL: Scaling LLMs with Reasoning Data and Test-Time Compute for Accurate RTL Code Generationcited by 22
  3. 2025DeepCircuitX: A Comprehensive Repository-Level Dataset for RTL Code Understanding, Generation, and PPA Analysiscited by 21
  4. 2024LLM4SecHW: Leveraging Domain Specific Large Language Model for Hardware Debuggingcited by 18
  5. 2024Automated C/C++ Program Repair for High-Level Synthesis via Large Language Modelscited by 18
  6. 2024LangProp: A code optimization framework using Large Language Models applied to drivingcited by 17
  7. 2025Spec2RTL-Agent: Automated Hardware Code Generation from Complex Specifications Using LLM Agent Systemscited by 17
  8. 2025RTL++: Graph-enhanced LLM for RTL Code Generationcited by 16
  9. 2025Language Models for Code Optimization: Survey, Challenges and Future Directionscited by 15
  10. 2025Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedbackcited by 14
  11. 2025VeriDebug: A Unified LLM for Verilog Debugging via Contrastive Embedding and Guided Correctioncited by 12
  12. 2024Evaluating Large Language Models for Automatic Register Transfer Logic Generation via High-Level Synthesiscited by 5
  13. 2025EvoVerilog: Large Langugage Model Assisted Evolution of Verilog Codecited by 2

Built on by

Cited by year (2026 to 7 Oct)

Citing papers per year: 2026: 3.

3 papers.

  1. 2026ARES: Adaptive Reasoning-Effort Steering for PPA- and Cost-Aware RTL Optimization with LLM Agentscited by 1
  2. 2026CLOSER-Bench: Evaluating Budgeted Cross-Stage Design Closure for Hardware Agentscited by 0
  3. 2026BEHAVE: Functional Behavior Modeling Enables Self-Improving Agents for Hardware Design and Verificationcited by 0