mlsanityData to 14 Oct 2026

QiMeng-CodeV-R1: Reasoning-Enhanced Verilog Generation

arXiv 2505.24183 ↗First posted 30 May 2025cs.LG cs.AR cs.PLcited by 35

On the map: LLM reasoning → Reasoning for agents, planning and code

Abstract (arXiv)

Large language models (LLMs) trained via reinforcement learning with verifiable reward (RLVR) have achieved breakthroughs on tasks with explicit, automatable verification, such as software programming and mathematical problems. Extending RLVR to electronic design automation (EDA), especially automatically generating hardware description languages (HDLs) like Verilog from natural-language (NL) specifications, however, poses three key challenges: the lack of automated and accurate verification environments, the scarcity of high-quality NL-code pairs, and the prohibitive computation cost of RLVR. To this end, we introduce CodeV-R1, an RLVR framework for training Verilog generation LLMs. First, we develop a rule-based testbench generator that performs robust equivalence checking against golden references. Second, we propose a round-trip data synthesis method that pairs open-source Verilog snippets with LLM-generated NL descriptions, verifies code-NL-code consistency via the generated testbench, and filters out inequivalent examples to yield a high-quality dataset. Third, we employ a two-stage "distill-then-RL" training pipeline: distillation for the cold start of reasoning abilities, followed by adaptive DAPO, our novel RLVR algorithm that can reduce training cost by adaptively adjusting sampling rate. The resulting model, CodeV-R1-7B, achieves 68.6% and 72.9% pass@1 on VerilogEval v2 and RTLLM v1.1, respectively, surpassing prior state-of-the-art by 12~20%, while even exceeding the performance of 671B DeepSeek-R1 on RTLLM. We have released our model, training code, and dataset to facilitate research in EDA and LLM communities.

Key facts. Cited by 35 papers in the map (data through 14 Oct 2026). Placed in Reasoning for agents, planning and code, one of 17 directions in LLM reasoning. Builds on 30 of its 50 references that are in the map. First posted on arXiv 30 May 2025.

Builds on

30 of 50 references.

Closest ancestors · 5

Same direction, newest first

  1. 2025ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model20 Apr
  2. 2025Fin-R1: A Large Language Model for Financial Reasoning through Reinforcement Learning20 Mar
  3. 2025KodCode: A Diverse, Challenging, and Verifiable Synthetic Dataset for Coding4 Mar
  4. 2024OpenAI o1 System Card21 Dec
  5. 2024Qwen2.5-Coder Technical Report18 Sep

Other references · 25

  1. 2021Evaluating Large Language Models Trained on Codecited by 8,320
  2. 2025DeepSeek-R1: Incentivizing Reasoning Capability in LLMs via Reinforcement Learningcited by 6,330
  3. 2024Qwen2.5 Technical Reportcited by 4,942
  4. 2024GPT-4o System Cardcited by 4,588
  5. 2025DAPO: An Open-Source LLM Reinforcement Learning System at Scalecited by 2,810
  6. 2024HybridFlow: A Flexible and Efficient RLHF Frameworkcited by 2,057
  7. 2025Search-R1: Training LLMs to Reason and Leverage Search Engines with Reinforcement Learningcited by 1,444
  8. 2025s1: Simple test-time scalingcited by 1,341
  9. 2025Kimi k1.5: Scaling Reinforcement Learning with LLMscited by 1,210
  10. 2021Measuring Coding Challenge Competence With APPScited by 902
  11. 2024DeepSeek-V3 Technical Reportcited by 811
  12. 2025SimpleRL-Zoo: Investigating and Taming Zero Reinforcement Learning for Open Base Models in the Wildcited by 511
13 more
  1. 2025LIMO: Less is More for Reasoningcited by 498
  2. 2025Open-Reasoner-Zero: An Open Source Approach to Scaling Up Reinforcement Learning on the Base Modelcited by 461
  3. 2022One Embedder, Any Task: Instruction-Finetuned Text Embeddingscited by 333
  4. 2025Logic-RL: Unleashing LLM Reasoning with Rule-Based Reinforcement Learningcited by 262
  5. 2024Imitate, Explore, and Self-Improve: A Reproduction Report on Slow-thinking Reasoning Systemscited by 164
  6. 2023TACO: Topics in Algorithmic COde generation datasetcited by 160
  7. 2024O1 Replication Journey -- Part 2: Surpassing O1-preview through Simple Distillation, Big Progress or Bitter Lesson?cited by 92
  8. 2024Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generationcited by 45
  9. 2024CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repaircited by 42
  10. 2024CodeV: Empowering LLMs with HDL Generation through Multi-Level Summarizationcited by 38
  11. 2024CorrectBench: Automatic Testbench Generation with Functional Self-Correction using LLMs for HDL Designcited by 24
  12. 2024Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learningcited by 15
  13. 2025Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedbackcited by 14

Built on by

Cited by year (2026 to 14 Oct)

Citing papers per year: 2025: 9; 2026: 26.

35 papers.

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By area:

  1. 2025A Survey of Reinforcement Learning for Large Reasoning Modelscited by 180
  2. 2025StepFun-Formalizer: Unlocking the Autoformalization Potential of LLMs through Knowledge-Reasoning Fusioncited by 16
  3. 2025AnalogCoder-Pro: Unifying Analog Circuit Generation and Optimization via Multi-modal LLMscited by 15
  4. 2025Understanding and Mitigating Errors of LLM-Generated RTL Codecited by 8
  5. 2025Large Language Model for Verilog Code Generation: Literature Review and the Road Aheadcited by 8
  6. 2025Replay Failures as Successes: Sample-Efficient Reinforcement Learning for Instruction Followingcited by 8
  7. 2026ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Designcited by 8
  8. 2025PRO-V-R1: Reasoning Enhanced Programming Agent for RTL Verificationcited by 7
  9. 2026EvolVE: Evolutionary Search for LLM-based Verilog Generation and Optimizationcited by 7
  10. 2026HardSecBench: Benchmarking the Security Awareness of LLMs for Hardware Code Generationcited by 5
  11. 2026LLM4Cov: Execution-Aware Agentic Learning for High-coverage Testbench Generationcited by 5
  12. 2026SiliconMind-V1: Multi-Agent Distillation and Debug-Reasoning Workflows for Verilog Code Generationcited by 4
23 more
  1. 2026InCoder-32B-Thinking: Industrial Code World Model for Thinkingcited by 4
  2. 2025Reasoner for Real-World Event Detection: Scaling Reinforcement Learning via Adaptive Perplexity-Aware Sampling Strategycited by 3
  3. 2026Veri-Sure: A Contract-Aware Multi-Agent Framework with Temporal Tracing and Formal Verification for Correct RTL Code Generationcited by 3
  4. 2026Semantic Consensus Decoding: Backdoor Defense for Verilog Code Generationcited by 3
  5. 2026COEVO: Co-Evolutionary Framework for Joint Functional Correctness and PPA Optimization in LLM-Based RTL Generationcited by 3
  6. 2026QiMeng-CodeV-SVA: Training Specialized LLMs for Hardware Assertion Generation via RTL-Grounded Bidirectional Data Synthesiscited by 2
  7. 2026UCAgent: An End-to-End Agent for Block-Level Functional Verificationcited by 2
  8. 2026QiMeng-PRepair: Precise Code Repair via Edit-Aware Reward Optimizationcited by 2
  9. 2026Structured Testbench Generation for LLM-Driven HDL Design and Verification-Oriented Data Curationcited by 2
  10. 2026QiMeng-ChipV-RTL: Exploiting Information Locality for IP-level Verilog Generationcited by 1
  11. 2026Internalizing Agency from Reflective Experiencecited by 1
  12. 2026CodePivot: Bootstrapping Multilingual Transpilation in LLMs via Reinforcement Learning without Parallel Corporacited by 1
  13. 2026RTL-BenchLS: A Large-Scale Benchmark for RTL Reasoning and Generation with Large Language Modelscited by 1
  14. 2025QiMeng: Fully Automated Hardware and Software Design for Processor Chipcited by 0
  15. 2026Exploring LLM-based Verilog Code Generation with Data-Efficient Fine-Tuning and Testbench Automationcited by 0
  16. 2026AutoPPA: Automated Circuit PPA Optimization via Contrastive Code-based Rule Library Learningcited by 0
  17. 2026From Mirage to Grounding: Towards Reliable Multimodal Circuit-to-Verilog Code Generationcited by 0
  18. 2026Natural Synthesis: Outperforming Reactive Synthesis Tools with Large Reasoning Modelscited by 0
  19. 2026CASS-RTL: Correctness-Aware Subspace Steering for RTL Generation with LLMscited by 0
  20. 2026Efficient Skill Grounding via Code Refactoring with Small Language Modelscited by 0
  21. 2026How LLMs Fail and Generalize in RTL Coding for Hardware Design?cited by 0
  22. 2026Multi-turn RL with Structural and Performance Aware Rewards for CUDA Kernel Generationcited by 0
  23. 2026CHORUS: Complementary Experts for High-Coverage Testbench Stimulus Generationcited by 0

Similar, not cited

Close in wording, no citation either way

  1. 2025VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning
  2. 2025VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation
  3. 2025QiMeng-SALV: Signal-Aware Learning for Verilog Code Generation
  4. 2026Automating Formal Verification with Reinforcement Learning and Recursive Inference
  5. 2026Knowledge-to-Verification: Exploring RLVR for LLMs in Knowledge-Intensive Domains
  6. 2025EARL: Entropy-Aware RL Alignment of LLMs for Reliable RTL Code Generation
  7. 2025VeriMind: Agentic LLM for Automated Verilog Generation with a Novel Evaluation Metric
  8. 2025VerIF: Verification Engineering for Reinforcement Learning in Instruction Following