CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design
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Abstract (arXiv)
The rapid advancements of AI rely on the support of ICs. However, the growing complexity of digital ICs makes the traditional IC design process costly and time-consuming. In recent years, AI-assisted IC design methods have demonstrated great potential, but most methods are task-specific or focus solely on the circuit structure in graph format, overlooking other circuit modalities with rich functional information. In this paper, we introduce CircuitFusion, the first multimodal and implementation-aware circuit encoder. It encodes circuits into general representations that support different downstream circuit design tasks. To learn from circuits, we propose to fuse three circuit modalities: hardware code, structural graph, and functionality summary. More importantly, we identify four unique properties of circuits: parallel execution, functional equivalent transformation, multiple design stages, and circuit reusability. Based on these properties, we propose new strategies for both the development and application of CircuitFusion: 1) During circuit preprocessing, utilizing the parallel nature of circuits, we split each circuit into multiple sub-circuits based on sequential-element boundaries, each sub-circuit in three modalities. 2) During CircuitFusion pre-training, we introduce three self-supervised tasks that utilize equivalent transformations both within and across modalities. 3) When applying CircuitFusion to downstream tasks, we propose a new retrieval-augmented inference method, which retrieves similar known circuits as a reference for predictions. It improves fine-tuning performance and even enables zero-shot inference. Evaluated on five different circuit design tasks, CircuitFusion consistently outperforms the SOTA supervised method specifically developed for every single task, demonstrating its generalizability and ability to learn circuits' inherent properties.
Key facts. Cited by 14 papers in the map (data through 7 Oct 2026). First posted on arXiv 4 May 2025.
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Citing papers per year: 2025: 6; 2026: 8.
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- 2025AnalogCoder-Pro: Unifying Analog Circuit Generation and Optimization via Multi-modal LLMscited by 14
- 2025Revolution or Hype? Seeking the Limits of Large Models in Hardware Designcited by 9
- 2025VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Codecited by 3
- 2025Alignment Unlocks Complementarity: A Framework for Multiview Circuit Representation Learningcited by 1
- 2025TRACE: Learning to Compute on Circuit Graphscited by 0
- 2025Learning Representations Through Contrastive Neural Model Checkingcited by 0
- 2026GNN-based Path-aware multi-view Circuit Learning for Technology Mappingcited by 0
- 2026Wrong Code, Right Structure: Learning Netlist Representations from Imperfect LLM-Generated RTLcited by 0
- 2026Graph Computation Meets Circuit Algebra: A Task-Aligned Analysis of Graph Neural Networks for Electronic Design Automationcited by 0
- 2026UniRTL: Unifying Code and Graph for Robust RTL Representation Learningcited by 0
- 2026RTL-Sequencer: Towards Scalable RTL Timing Prediction with the Sequence-based Paradigmcited by 0
- 2026RTLCurator: Label-Efficient Data Curation for RTL Generationcited by 0
- 2026LevelSyn: Physical-Aware Logic Synthesis via Level-Asynchronous Graph Neural Networks3 Sep 2026
- 2026Beyond Flat Netlist: Hierarchical Graph Representation Learning for Scalable Analysis of Sequential Circuits28 Aug 2026
- 2026RTLCurator: Label-Efficient Data Curation for RTL Generation31 Jul 2026
- 2026RTL-Sequencer: Towards Scalable RTL Timing Prediction with the Sequence-based Paradigm17 Jul 2026
- 2026UniRTL: Unifying Code and Graph for Robust RTL Representation Learning29 May 2026
- 2026Graph Computation Meets Circuit Algebra: A Task-Aligned Analysis of Graph Neural Networks for Electronic Design Automation8 May 2026
- 2026Wrong Code, Right Structure: Learning Netlist Representations from Imperfect LLM-Generated RTL10 Mar 2026
- 2026GNN-based Path-aware multi-view Circuit Learning for Technology Mapping14 Jan 2026
- 2025Learning Representations Through Contrastive Neural Model Checking2 Oct 2025
- 2025TRACE: Learning to Compute on Circuit Graphs26 Sep 2025
- 2025Alignment Unlocks Complementarity: A Framework for Multiview Circuit Representation Learning25 Sep 2025
- 2025Revolution or Hype? Seeking the Limits of Large Models in Hardware Design5 Sep 2025
- 2025AnalogCoder-Pro: Unifying Analog Circuit Generation and Optimization via Multi-modal LLMscited by 14
- 2025Revolution or Hype? Seeking the Limits of Large Models in Hardware Designcited by 9
- 2025VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Codecited by 3
- 2025Alignment Unlocks Complementarity: A Framework for Multiview Circuit Representation Learningcited by 1
- 2025TRACE: Learning to Compute on Circuit Graphscited by 0
- 2025Learning Representations Through Contrastive Neural Model Checkingcited by 0
- 2026GNN-based Path-aware multi-view Circuit Learning for Technology Mappingcited by 0
- 2026Wrong Code, Right Structure: Learning Netlist Representations from Imperfect LLM-Generated RTLcited by 0
- 2026Graph Computation Meets Circuit Algebra: A Task-Aligned Analysis of Graph Neural Networks for Electronic Design Automationcited by 0
- 2026UniRTL: Unifying Code and Graph for Robust RTL Representation Learningcited by 0
- 2026RTL-Sequencer: Towards Scalable RTL Timing Prediction with the Sequence-based Paradigmcited by 0
- 2026RTLCurator: Label-Efficient Data Curation for RTL Generationcited by 0
12 most cited of 14 All 14 (JSON)
- 2026LevelSyn: Physical-Aware Logic Synthesis via Level-Asynchronous Graph Neural Networks3 Sep 2026
- 2026Beyond Flat Netlist: Hierarchical Graph Representation Learning for Scalable Analysis of Sequential Circuits28 Aug 2026
- 2026RTLCurator: Label-Efficient Data Curation for RTL Generation31 Jul 2026
- 2026RTL-Sequencer: Towards Scalable RTL Timing Prediction with the Sequence-based Paradigm17 Jul 2026
- 2026UniRTL: Unifying Code and Graph for Robust RTL Representation Learning29 May 2026
- 2026Graph Computation Meets Circuit Algebra: A Task-Aligned Analysis of Graph Neural Networks for Electronic Design Automation8 May 2026
- 2026Wrong Code, Right Structure: Learning Netlist Representations from Imperfect LLM-Generated RTL10 Mar 2026
- 2026GNN-based Path-aware multi-view Circuit Learning for Technology Mapping14 Jan 2026
- 2025Learning Representations Through Contrastive Neural Model Checking2 Oct 2025
- 2025TRACE: Learning to Compute on Circuit Graphs26 Sep 2025
- 2025Alignment Unlocks Complementarity: A Framework for Multiview Circuit Representation Learning25 Sep 2025
- 2025Revolution or Hype? Seeking the Limits of Large Models in Hardware Design5 Sep 2025
12 newest of 14 All 14 (JSON)
Similar, not cited
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- 2025NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph
- 2025DeepGate4: Efficient and Effective Representation Learning for Circuit Design at Scale
- 2025Circuit Representation Learning with Masked Gate Modeling and Verilog-AIG Alignment
- 2024AnalogCoder: Analog Circuit Design via Training-Free Code Generation
- 2025TopoSizing: An LLM-aided Framework of Topology-based Understanding and Sizing for AMS Circuits
- 2026AnalogRetriever: Learning Cross-Modal Representations for Analog Circuit Retrieval
- 2025SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuits
- 2024AnalogXpert: Automating Analog Topology Synthesis by Incorporating Circuit Design Expertise into Large Language Models