mlsanityData to 14 Oct 2026

A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDA

arXiv 2504.03711 ↗First posted 28 Mar 2025cs.AR cs.LGcited by 17

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Abstract (arXiv)

Artificial intelligence (AI)-driven electronic design automation (EDA) techniques have been extensively explored for VLSI circuit design applications. Most recently, foundation AI models for circuits have emerged as a new technology trend. Unlike traditional task-specific AI solutions, these new AI models are developed through two stages: 1) self-supervised pre-training on a large amount of unlabeled data to learn intrinsic circuit properties; and 2) efficient fine-tuning for specific downstream applications, such as early-stage design quality evaluation, circuit-related context generation, and functional verification. This new paradigm brings many advantages: model generalization, less reliance on labeled circuit data, efficient adaptation to new tasks, and unprecedented generative capability. In this paper, we propose referring to AI models developed with this new paradigm as circuit foundation models (CFMs). This paper provides a comprehensive survey of the latest progress in circuit foundation models, unprecedentedly covering over 130 relevant works. Over 90% of our introduced works were published in or after 2022, indicating that this emerging research trend has attracted wide attention in a short period. In this survey, we propose to categorize all existing circuit foundation models into two primary types: 1) encoder-based methods performing general circuit representation learning for predictive tasks; and 2) decoder-based methods leveraging large language models (LLMs) for generative tasks. For our introduced works, we cover their input modalities, model architecture, pre-training strategies, domain adaptation techniques, and downstream design applications. In addition, this paper discussed the unique properties of circuits from the data perspective. These circuit properties have motivated many works in this domain and differentiated them from general AI techniques.

Key facts. Cited by 17 papers in the map (data through 14 Oct 2026). Builds on 10 of its 28 references that are in the map. First posted on arXiv 28 Mar 2025.

Builds on

10 of 28 references.

References · 10

  1. 2021Prompt Programming for Large Language Models: Beyond the Few-Shot Paradigmcited by 606
  2. 2024RTLRewriter: Methodologies for Large Models aided RTL Code Optimizationcited by 31
  3. 2024HLSPilot: LLM-based High-Level Synthesiscited by 25
  4. 2024Rome was Not Built in a Single Step: Hierarchical Prompting for LLM-based Chip Designcited by 24
  5. 2024Automatically Improving LLM-based Verilog Generation using EDA Tool Feedbackcited by 19
  6. 2024AssertionBench: A Benchmark to Evaluate Large-Language Models for Assertion Generationcited by 16
  7. 2025Enhancing Large Language Models for Hardware Verification: A Novel SystemVerilog Assertion Datasetcited by 10
  8. 2023HW-V2W-Map: Hardware Vulnerability to Weakness Mapping Framework for Root Cause Analysis with GPT-assisted Mitigation Suggestioncited by 8
  9. 2025LintLLM: An Open-Source Verilog Linting Framework Based on Large Language Modelscited by 7
  10. 2024Are LLMs Any Good for High-Level Synthesis?cited by 6

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Cited by year (2026 to 14 Oct)

Citing papers per year: 2025: 13; 2026: 4.

17 papers.

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  1. 2025AMSbench: A Comprehensive Benchmark for Evaluating MLLM Capabilities in AMS Circuitscited by 15
  2. 2025AnalogCoder-Pro: Unifying Analog Circuit Generation and Optimization via Multi-modal LLMscited by 15
  3. 2025NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graphcited by 9
  4. 2025Large Language Model for Verilog Code Generation: Literature Review and the Road Aheadcited by 8
  5. 2025AutoEDA: Enabling EDA Flow Automation through Microservice-Based LLM Agentscited by 6
  6. 2026Dr. RTL: Autonomous Agentic RTL Optimization through Tool-Grounded Self-Improvementcited by 6
  7. 2025Discovering heuristics in a complex SAT solver with large language modelscited by 4
  8. 2026OSIRIS: Bridging Analog Circuit Design and Machine Learning with Scalable Dataset Generationcited by 3
  9. 2025AgenticTCAD: A LLM-based Multi-Agent Framework for Automated TCAD Code Generation and Device Optimizationcited by 2
  10. 2025GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignmentcited by 1
  11. 2025FuncGNN: Learning Functional Semantics of Logic Circuits with Graph Neural Networkscited by 1
  12. 2025Modeling Relational Logic Circuits for And-Inverter Graph Convolutional Networkcited by 0
5 more
  1. 2025SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuitscited by 0
  2. 2025ParaGate: Parasitic-Driven Domain Adaptation Transfer Learning for Netlist Performance Predictioncited by 0
  3. 2025AMS-IO-Bench and AMS-IO-Agent: Benchmarking and Structured Reasoning for Analog and Mixed-Signal Integrated Circuit Input/Output Designcited by 0
  4. 2026Agentic Electronic Design Automation: A Handoff Perspectivecited by 0
  5. 2026Fine-Tuning of Transformer models with Framescited by 0