mlsanityData to 14 Oct 2026

NotSoTiny: A Large, Living Benchmark for RTL Code Generation

arXiv 2512.20823 ↗First posted 23 Dec 2025cs.AR cs.AIcited by 4

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Abstract (arXiv)

LLMs have shown early promise in generating RTL code, yet evaluating their capabilities in realistic setups remains a challenge. So far, RTL benchmarks have been limited in scale, skewed toward trivial designs, offering minimal verification rigor, and remaining vulnerable to data contamination. To overcome these limitations and to push the field forward, this paper introduces NotSoTiny, a benchmark that assesses LLM on the generation of structurally rich and context-aware RTL. Built from hundreds of actual hardware designs produced by the Tiny Tapeout community, our automated pipeline removes duplicates, verifies correctness and periodically incorporates new designs to mitigate contamination, matching Tiny Tapeout release schedule. Evaluation results show that NotSoTiny tasks are more challenging than prior benchmarks, emphasizing its effectiveness in overcoming current limitations of LLMs applied to hardware design, and in guiding the improvement of such promising technology.

Key facts. Cited by 4 papers in the map (data through 14 Oct 2026). Builds on 13 of its 29 references that are in the map. First posted on arXiv 23 Dec 2025.

Builds on

13 of 29 references.

References · 13

  1. 2024The Llama 3 Herd of Modelscited by 14,715
  2. 2021Evaluating Large Language Models Trained on Codecited by 8,320
  3. 2024Qwen2.5 Technical Reportcited by 4,942
  4. 2025gpt-oss-120b & gpt-oss-20b Model Cardcited by 1,386
  5. 2024LiveBench: A Challenging, Contamination-Limited LLM Benchmarkcited by 262
  6. 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 252
  7. 2024Generalization or Memorization: Data Contamination and Trustworthy Evaluation for Large Language Modelscited by 122
  8. 2024Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generationcited by 45
  9. 2025A Survey of Research in Large Language Models for Electronic Design Automationcited by 41
  10. 2025HaVen: Hallucination-Mitigated LLM for Verilog Code Generation Aligned with HDL Engineerscited by 25
  11. 2024Towards Data Contamination Detection for Modern Large Language Models: Limitations, Inconsistencies, and Oracle Challengescited by 18
  12. 2025VeriContaminated: Assessing LLM-Driven Verilog Coding for Data Contaminationcited by 12
1 more
  1. 2025TuRTLe: A Unified Evaluation of LLMs for RTL Generationcited by 9

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Cited by year (2026 to 14 Oct)

Citing papers per year: 2026: 4.

4 papers.