NotSoTiny: A Large, Living Benchmark for RTL Code Generation
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Abstract (arXiv)
LLMs have shown early promise in generating RTL code, yet evaluating their capabilities in realistic setups remains a challenge. So far, RTL benchmarks have been limited in scale, skewed toward trivial designs, offering minimal verification rigor, and remaining vulnerable to data contamination. To overcome these limitations and to push the field forward, this paper introduces NotSoTiny, a benchmark that assesses LLM on the generation of structurally rich and context-aware RTL. Built from hundreds of actual hardware designs produced by the Tiny Tapeout community, our automated pipeline removes duplicates, verifies correctness and periodically incorporates new designs to mitigate contamination, matching Tiny Tapeout release schedule. Evaluation results show that NotSoTiny tasks are more challenging than prior benchmarks, emphasizing its effectiveness in overcoming current limitations of LLMs applied to hardware design, and in guiding the improvement of such promising technology.
Key facts. Cited by 4 papers in the map (data through 14 Oct 2026). Builds on 13 of its 29 references that are in the map. First posted on arXiv 23 Dec 2025.
Builds on
13 of 29 references.
References · 13
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1 more
- 2025TuRTLe: A Unified Evaluation of LLMs for RTL Generationcited by 9
Built on by
Citing papers per year: 2026: 4.
4 papers.
- 2026Exploring the Agentic Frontier of Verilog Code Generationcited by 1
- 2026RuC: HDL-Agnostic Rule Completion Benchmark Generationcited by 0
- 2026BEHAVE: Functional Behavior Modeling Enables Self-Improving Agents for Hardware Design and Verificationcited by 0
- 2026SGAnalog: An End-to-End Circuit Benchmark from Open-Source Silicon Tapeoutscited by 0
- 2026SGAnalog: An End-to-End Circuit Benchmark from Open-Source Silicon Tapeouts2 Oct 2026
- 2026BEHAVE: Functional Behavior Modeling Enables Self-Improving Agents for Hardware Design and Verification28 Sep 2026
- 2026RuC: HDL-Agnostic Rule Completion Benchmark Generation30 Apr 2026
- 2026Exploring the Agentic Frontier of Verilog Code Generation19 Mar 2026