The Dawn of AI-Native EDA: Opportunities and Challenges of Large Circuit Models
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Abstract (arXiv)
Within the Electronic Design Automation (EDA) domain, AI-driven solutions have emerged as formidable tools, yet they typically augment rather than redefine existing methodologies. These solutions often repurpose deep learning models from other domains, such as vision, text, and graph analytics, applying them to circuit design without tailoring to the unique complexities of electronic circuits. Such an AI4EDA approach falls short of achieving a holistic design synthesis and understanding, overlooking the intricate interplay of electrical, logical, and physical facets of circuit data. This paper argues for a paradigm shift from AI4EDA towards AI-native EDA, integrating AI at the core of the design process. Pivotal to this vision is the development of a multimodal circuit representation learning technique, poised to provide a comprehensive understanding by harmonizing and extracting insights from varied data sources, such as functional specifications, RTL designs, circuit netlists, and physical layouts. We champion the creation of large circuit models (LCMs) that are inherently multimodal, crafted to decode and express the rich semantics and structures of circuit data, thus fostering more resilient, efficient, and inventive design methodologies. Embracing this AI-native philosophy, we foresee a trajectory that transcends the current innovation plateau in EDA, igniting a profound shift-left in electronic design methodology. The envisioned advancements herald not just an evolution of existing EDA tools but a revolution, giving rise to novel instruments of design tools that promise to radically enhance design productivity and inaugurate a new epoch where the optimization of circuit performance, power, and area (PPA) is achieved not incrementally, but through leaps that redefine the benchmarks of electronic systems' capabilities.
Key facts. Cited by 12 papers in the map (data through 7 Oct 2026). First posted on arXiv 12 Mar 2024.
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Citing papers per year: 2024: 1; 2025: 8; 2026: 3.
12 papers.
- 2025NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graphcited by 9
- 2025Revolution or Hype? Seeking the Limits of Large Models in Hardware Designcited by 9
- 2025Large Language Model for Verilog Code Generation: Literature Review and the Road Aheadcited by 7
- 2025MMCircuitEval: A Comprehensive Multimodal Circuit-Focused Benchmark for Evaluating LLMscited by 6
- 2024SemiKong: Curating, Training, and Evaluating A Semiconductor Industry-Specific Large Language Modelcited by 4
- 2025DeepCell: Self-Supervised Multiview Fusion for Circuit Representation Learningcited by 3
- 2025GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignmentcited by 1
- 2025Alignment Unlocks Complementarity: A Framework for Multiview Circuit Representation Learningcited by 1
- 2025Learning Library Cell Representations in Vector Spacecited by 0
- 2026RulePlanner: All-in-One Reinforcement Learner for Unifying Design Rules in 3D Floorplanningcited by 0
- 2026AutoVSR: Automatic Visual-to-Symbolic Reasoning for Symbolic Expression Generation from Circuit Schematiccited by 0
- 2026LLMs in Digital EDA: A perspective on shifting roles from Generation to Orchestrationcited by 0
- 2026LLMs in Digital EDA: A perspective on shifting roles from Generation to Orchestration27 Aug 2026
- 2026AutoVSR: Automatic Visual-to-Symbolic Reasoning for Symbolic Expression Generation from Circuit Schematic13 Jul 2026
- 2026RulePlanner: All-in-One Reinforcement Learner for Unifying Design Rules in 3D Floorplanning30 Jan 2026
- 2025Large Language Model for Verilog Code Generation: Literature Review and the Road Ahead29 Oct 2025
- 2025Alignment Unlocks Complementarity: A Framework for Multiview Circuit Representation Learning25 Sep 2025
- 2025Revolution or Hype? Seeking the Limits of Large Models in Hardware Design5 Sep 2025
- 2025MMCircuitEval: A Comprehensive Multimodal Circuit-Focused Benchmark for Evaluating LLMs20 Jul 2025
- 2025GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignment13 Apr 2025
- 2025NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph12 Apr 2025
- 2025Learning Library Cell Representations in Vector Space28 Mar 2025
- 2025DeepCell: Self-Supervised Multiview Fusion for Circuit Representation Learning5 Feb 2025
- 2024SemiKong: Curating, Training, and Evaluating A Semiconductor Industry-Specific Large Language Model21 Nov 2024