RTLSquad: Multi-Agent Based Interpretable RTL Design
On the map: LLM agents and tool use → Software engineering coding agents
Abstract (arXiv)
Optimizing Register-Transfer Level (RTL) code is crucial for improving hardware PPA performance. Large Language Models (LLMs) offer new approaches for automatic RTL code generation and optimization. However, existing methods often lack decision interpretability (sufficient, understandable justification for decisions), making it difficult for hardware engineers to trust the generated results, thus preventing these methods from being integrated into the design process. To address this, we propose RTLSquad, a novel LLM-Based Multi-Agent system for interpretable RTL code generation. RTLSquad divides the design process into exploration, implementation, and verification & evaluation stages managed by specialized agent squads, generating optimized RTL code through inter-agent collaboration, and providing decision interpretability through the communication process. Experiments show that RTLSquad excels in generating functionally correct RTL code and optimizing PPA performance, while also having the capability to provide decision paths, demonstrating the practical value of our system.
Key facts. Cited by 9 papers in the map (data through 7 Oct 2026). Placed in Software engineering coding agents, one of 16 directions in LLM agents and tool use. First posted on arXiv 6 Jan 2025.
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Citing papers per year: 2025: 4; 2026: 5.
9 papers.
- 2025Large Language Model for Verilog Code Generation: Literature Review and the Road Aheadcited by 7
- 2026EvolVE: Evolutionary Search for LLM-based Verilog Generation and Optimizationcited by 7
- 2025Towards Optimal Circuit Generation: Multi-Agent Collaboration Meets Collective Intelligencecited by 1
- 2025CRADLE: Conversational RTL Design Space Exploration with LLM-based Multi-Agent Systemscited by 1
- 2025Automating Hardware Design and Verification from Architectural Papers via a Neural-Symbolic Graph Frameworkcited by 1
- 2026QiMeng-ChipV-RTL: Exploiting Information Locality for IP-level Verilog Generationcited by 1
- 2026Agentic Electronic Design Automation: A Handoff Perspectivecited by 0
- 2026When LLMs Over-Answer: Measuring and Mitigating Quality Issues in LLM-Based Hardware Description Language Question Answeringcited by 0
- 2026LLMs in Digital EDA: A perspective on shifting roles from Generation to Orchestrationcited by 0
- 2026LLMs in Digital EDA: A perspective on shifting roles from Generation to Orchestration27 Aug 2026
- 2026When LLMs Over-Answer: Measuring and Mitigating Quality Issues in LLM-Based Hardware Description Language Question Answering19 Jul 2026
- 2026Agentic Electronic Design Automation: A Handoff Perspective18 Jun 2026
- 2026QiMeng-ChipV-RTL: Exploiting Information Locality for IP-level Verilog Generation31 Jan 2026
- 2026EvolVE: Evolutionary Search for LLM-based Verilog Generation and Optimization26 Jan 2026
- 2025Automating Hardware Design and Verification from Architectural Papers via a Neural-Symbolic Graph Framework8 Nov 2025
- 2025Large Language Model for Verilog Code Generation: Literature Review and the Road Ahead29 Oct 2025
- 2025CRADLE: Conversational RTL Design Space Exploration with LLM-based Multi-Agent Systems12 Aug 2025
- 2025Towards Optimal Circuit Generation: Multi-Agent Collaboration Meets Collective Intelligence20 Apr 2025
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- 2026CODMAS: A Dialectic Multi-Agent Collaborative Framework for Structured RTL Optimization
- 2025PEFA-AI: Advancing Open-source LLMs for RTL generation using Progressive Error Feedback Agentic-AI
- 2026VeriAgent: A Tool-Integrated Multi-Agent System with Evolving Memory for PPA-Aware RTL Code Generation
- 2026ACE-RTL: When Agentic Context Evolution Meets RTL-Specialized LLMs
- 2025Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification
- 2024EDA-Aware RTL Generation with Large Language Models
- 2026Can Agents Design Better Chips with a Higher Level Abstraction?
- 2025DUET: Agentic Design Understanding via Experimentation and Testing