mlsanityData to 7 Oct 2026

Exploring Code Language Models for Automated HLS-based Hardware Generation: Benchmark, Infrastructure and Analysis

arXiv 2502.13921 ↗First posted 19 Feb 2025cs.LG cs.AR cs.SEcited by 10

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Abstract (arXiv)

Recent advances in code generation have illuminated the potential of employing large language models (LLMs) for general-purpose programming languages such as Python and C++, opening new opportunities for automating software development and enhancing programmer productivity. The potential of LLMs in software programming has sparked significant interest in exploring automated hardware generation and automation. Although preliminary endeavors have been made to adopt LLMs in generating hardware description languages (HDLs), several challenges persist in this direction. First, the volume of available HDL training data is substantially smaller compared to that for software programming languages. Second, the pre-trained LLMs, mainly tailored for software code, tend to produce HDL designs that are more error-prone. Third, the generation of HDL requires a significantly higher number of tokens compared to software programming, leading to inefficiencies in cost and energy consumption. To tackle these challenges, this paper explores leveraging LLMs to generate High-Level Synthesis (HLS)-based hardware design. Although code generation for domain-specific programming languages is not new in the literature, we aim to provide experimental results, insights, benchmarks, and evaluation infrastructure to investigate the suitability of HLS over low-level HDLs for LLM-assisted hardware design generation. To achieve this, we first finetune pre-trained models for HLS-based hardware generation, using a collected dataset with text prompts and corresponding reference HLS designs. An LLM-assisted framework is then proposed to automate end-to-end hardware code generation, which also investigates the impact of chain-of-thought and feedback loops promoting techniques on HLS-design generation. Limited by the timeframe of this research, we plan to evaluate more advanced reasoning models in the future.

Key facts. Cited by 10 papers in the map (data through 7 Oct 2026). Builds on 17 of its 31 references that are in the map. First posted on arXiv 19 Feb 2025.

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17 of 31 references.

References · 17

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5 more
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Cited by year (2026 to 7 Oct)

Citing papers per year: 2025: 4; 2026: 6.

10 papers.

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  1. 2025Large Language Model for Verilog Code Generation: Literature Review and the Road Ahead
  2. 2025HDLCoRe: A Training-Free Framework for Mitigating Hallucinations in LLM-Generated HDL
  3. 2025SAGE-HLS: Syntax-Aware AST-Guided LLM for High-Level Synthesis Code Generation
  4. 2026LLM4RTL: Tool-Assisted LLM for RTL Generation
  5. 2024AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMs
  6. 2025Holistic Evaluation of State-of-the-Art LLMs for Code Generation
  7. 2024Optimizing High-Level Synthesis Designs with Retrieval-Augmented Large Language Models
  8. 2026Exploring the Role of LLMs in HPC Programming: A Survey