DeepGate2: Functionality-Aware Circuit Representation Learning
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Abstract (arXiv)
Circuit representation learning aims to obtain neural representations of circuit elements and has emerged as a promising research direction that can be applied to various EDA and logic reasoning tasks. Existing solutions, such as DeepGate, have the potential to embed both circuit structural information and functional behavior. However, their capabilities are limited due to weak supervision or flawed model design, resulting in unsatisfactory performance in downstream tasks. In this paper, we introduce DeepGate2, a novel functionality-aware learning framework that significantly improves upon the original DeepGate solution in terms of both learning effectiveness and efficiency. Our approach involves using pairwise truth table differences between sampled logic gates as training supervision, along with a well-designed and scalable loss function that explicitly considers circuit functionality. Additionally, we consider inherent circuit characteristics and design an efficient one-round graph neural network (GNN), resulting in an order of magnitude faster learning speed than the original DeepGate solution. Experimental results demonstrate significant improvements in two practical downstream tasks: logic synthesis and Boolean satisfiability solving. The code is available at https://github.com/cure-lab/DeepGate2
Key facts. Cited by 33 papers in the map (data through 14 Oct 2026). Builds on 11 of its 40 references that are in the map. First posted on arXiv 25 May 2023.
Builds on
11 of 40 references.
References · 11
- 2017Attention Is All You Needcited by 60,361
- 2018BERT: Pre-training of Deep Bidirectional Transformers for Language Understandingcited by 40,399
- 2014Adam: A Method for Stochastic Optimizationcited by 37,240
- 2020Language Models are Few-Shot Learnerscited by 32,419
- 2018Unsupervised Feature Learning via Non-Parametric Instance-level Discriminationcited by 1,845
- 2017An Overview of Multi-Task Learning in Deep Neural Networkscited by 803
- 2014Deep metric learning using Triplet networkcited by 422
- 2022MaskPlace: Fast Chip Placement via Reinforced Visual Representation Learningcited by 43
- 2021DeepGate: Learning Neural Representations of Logic Gatescited by 37
- 2022DeepTPI: Test Point Insertion with Deep Reinforcement Learningcited by 10
- 2022TAG: Learning Circuit Spatial Embedding From Layoutscited by 9
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Citing papers per year: 2023: 2; 2024: 6; 2025: 17; 2026: 8.
33 papers.
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- 2023LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automationcited by 40
- 2024DeepGate3: Towards Scalable Circuit Representation Learningcited by 26
- 2025DeepCircuitX: A Comprehensive Repository-Level Dataset for RTL Code Understanding, Generation, and PPA Analysiscited by 21
- 2024VerilogReader: LLM-Aided Hardware Test Generationcited by 17
- 2025DeepGate4: Efficient and Effective Representation Learning for Circuit Design at Scalecited by 12
- 2024Retrieval-Guided Reinforcement Learning for Boolean Circuit Minimizationcited by 10
- 2025NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graphcited by 9
- 2025Circuit Representation Learning with Masked Gate Modeling and Verilog-AIG Alignmentcited by 8
- 2025MMCircuitEval: A Comprehensive Multimodal Circuit-Focused Benchmark for Evaluating LLMscited by 6
- 2023Verilog-to-PyG -- A Framework for Graph Learning and Augmentation on RTL Designscited by 5
- 2024DeepSeq2: Enhanced Sequential Circuit Learning with Disentangled Representationscited by 5
- 2025DeepCell: Self-Supervised Multiview Fusion for Circuit Representation Learningcited by 3
21 more
- 2025DICE: Device-level Integrated Circuits Encoder with Graph Contrastive Pretrainingcited by 2
- 2025Circuit-Aware SAT Solving: Guiding CDCL via Conditional Probabilitiescited by 2
- 2024Logic Synthesis Optimization with Predictive Self-Supervision via Causal Transformerscited by 1
- 2025GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignmentcited by 1
- 2025Functional Matching of Logic Subgraphs: Beyond Structural Isomorphismcited by 1
- 2025FuncGNN: Learning Functional Semantics of Logic Circuits with Graph Neural Networkscited by 1
- 2025Alignment Unlocks Complementarity: A Framework for Multiview Circuit Representation Learningcited by 1
- 2026R2G: A Multi-View Circuit Graph Benchmark Suite from RTL to GDSIIcited by 1
- 2024SiHGNN: Leveraging Properties of Semantic Graphs for Efficient HGNN Accelerationcited by 0
- 2025Learning Library Cell Representations in Vector Spacecited by 0
- 2025Modeling Relational Logic Circuits for And-Inverter Graph Convolutional Networkcited by 0
- 2025TRACE: Learning to Compute on Circuit Graphscited by 0
- 2025BoolSkeleton: Boolean Network Skeletonization via Homogeneous Pattern Reductioncited by 0
- 2025InF-ATPG: Intelligent FFR-Driven ATPG with Advanced Circuit Representation Guided Reinforcement Learningcited by 0
- 2026GNN-based Path-aware multi-view Circuit Learning for Technology Mappingcited by 0
- 2026MPBMC: Multi-Property Bounded Model Checking with GNN-guided Clusteringcited by 0
- 2026Wrong Code, Right Structure: Learning Netlist Representations from Imperfect LLM-Generated RTLcited by 0
- 2026Graph Computation Meets Circuit Algebra: A Task-Aligned Analysis of Graph Neural Networks for Electronic Design Automationcited by 0
- 2026Beyond Flat Netlist: Hierarchical Graph Representation Learning for Scalable Analysis of Sequential Circuitscited by 0
- 2026LevelSyn: Physical-Aware Logic Synthesis via Level-Asynchronous Graph Neural Networkscited by 0
- 2026ReDIL-GNN: Resynthesis Domain Incremental Learning for Circuit Graph Neural Networkscited by 0
- 2026ReDIL-GNN: Resynthesis Domain Incremental Learning for Circuit Graph Neural Networks16 Sep 2026
- 2026LevelSyn: Physical-Aware Logic Synthesis via Level-Asynchronous Graph Neural Networks3 Sep 2026
- 2026Beyond Flat Netlist: Hierarchical Graph Representation Learning for Scalable Analysis of Sequential Circuits28 Aug 2026
- 2026Graph Computation Meets Circuit Algebra: A Task-Aligned Analysis of Graph Neural Networks for Electronic Design Automation8 May 2026
- 2026R2G: A Multi-View Circuit Graph Benchmark Suite from RTL to GDSII9 Apr 2026
- 2026Wrong Code, Right Structure: Learning Netlist Representations from Imperfect LLM-Generated RTL10 Mar 2026
- 2026MPBMC: Multi-Property Bounded Model Checking with GNN-guided Clustering26 Feb 2026
- 2026GNN-based Path-aware multi-view Circuit Learning for Technology Mapping14 Jan 2026
- 2025InF-ATPG: Intelligent FFR-Driven ATPG with Advanced Circuit Representation Guided Reinforcement Learning25 Nov 2025
- 2025BoolSkeleton: Boolean Network Skeletonization via Homogeneous Pattern Reduction4 Nov 2025
- 2025TRACE: Learning to Compute on Circuit Graphs26 Sep 2025
- 2025Alignment Unlocks Complementarity: A Framework for Multiview Circuit Representation Learning25 Sep 2025
21 more
- 2025Modeling Relational Logic Circuits for And-Inverter Graph Convolutional Network16 Aug 2025
- 2025Circuit-Aware SAT Solving: Guiding CDCL via Conditional Probabilities6 Aug 2025
- 2025MMCircuitEval: A Comprehensive Multimodal Circuit-Focused Benchmark for Evaluating LLMs20 Jul 2025
- 2025FuncGNN: Learning Functional Semantics of Logic Circuits with Graph Neural Networks7 Jun 2025
- 2025Functional Matching of Logic Subgraphs: Beyond Structural Isomorphism28 May 2025
- 2025GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignment13 Apr 2025
- 2025NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph12 Apr 2025
- 2025Learning Library Cell Representations in Vector Space28 Mar 2025
- 2025DeepCircuitX: A Comprehensive Repository-Level Dataset for RTL Code Understanding, Generation, and PPA Analysis25 Feb 2025
- 2025Circuit Representation Learning with Masked Gate Modeling and Verilog-AIG Alignment18 Feb 2025
- 2025DICE: Device-level Integrated Circuits Encoder with Graph Contrastive Pretraining13 Feb 2025
- 2025DeepCell: Self-Supervised Multiview Fusion for Circuit Representation Learning5 Feb 2025
- 2025DeepGate4: Efficient and Effective Representation Learning for Circuit Design at Scale2 Feb 2025
- 2024DeepSeq2: Enhanced Sequential Circuit Learning with Disentangled Representations1 Nov 2024
- 2024Logic Synthesis Optimization with Predictive Self-Supervision via Causal Transformers16 Sep 2024
- 2024SiHGNN: Leveraging Properties of Semantic Graphs for Efficient HGNN Acceleration27 Aug 2024
- 2024DeepGate3: Towards Scalable Circuit Representation Learning15 Jul 2024
- 2024VerilogReader: LLM-Aided Hardware Test Generation3 Jun 2024
- 2024Retrieval-Guided Reinforcement Learning for Boolean Circuit Minimization22 Jan 2024
- 2023LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automation28 Dec 2023
- 2023Verilog-to-PyG -- A Framework for Graph Learning and Augmentation on RTL Designs9 Nov 2023
- 2023LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automationcited by 40
- 2024DeepGate3: Towards Scalable Circuit Representation Learningcited by 26
- 2025DeepCircuitX: A Comprehensive Repository-Level Dataset for RTL Code Understanding, Generation, and PPA Analysiscited by 21
- 2024VerilogReader: LLM-Aided Hardware Test Generationcited by 17
- 2025DeepGate4: Efficient and Effective Representation Learning for Circuit Design at Scalecited by 12
- 2025NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graphcited by 9
- 2025Circuit Representation Learning with Masked Gate Modeling and Verilog-AIG Alignmentcited by 8
- 2023Verilog-to-PyG -- A Framework for Graph Learning and Augmentation on RTL Designscited by 5
- 2024DeepSeq2: Enhanced Sequential Circuit Learning with Disentangled Representationscited by 5
- 2025DeepCell: Self-Supervised Multiview Fusion for Circuit Representation Learningcited by 3
- 2025DICE: Device-level Integrated Circuits Encoder with Graph Contrastive Pretrainingcited by 2
- 2025Circuit-Aware SAT Solving: Guiding CDCL via Conditional Probabilitiescited by 2
12 most cited of 30 All 30 (JSON)
- 2026ReDIL-GNN: Resynthesis Domain Incremental Learning for Circuit Graph Neural Networks16 Sep 2026
- 2026LevelSyn: Physical-Aware Logic Synthesis via Level-Asynchronous Graph Neural Networks3 Sep 2026
- 2026Beyond Flat Netlist: Hierarchical Graph Representation Learning for Scalable Analysis of Sequential Circuits28 Aug 2026
- 2026Graph Computation Meets Circuit Algebra: A Task-Aligned Analysis of Graph Neural Networks for Electronic Design Automation8 May 2026
- 2026R2G: A Multi-View Circuit Graph Benchmark Suite from RTL to GDSII9 Apr 2026
- 2026Wrong Code, Right Structure: Learning Netlist Representations from Imperfect LLM-Generated RTL10 Mar 2026
- 2026MPBMC: Multi-Property Bounded Model Checking with GNN-guided Clustering26 Feb 2026
- 2026GNN-based Path-aware multi-view Circuit Learning for Technology Mapping14 Jan 2026
- 2025InF-ATPG: Intelligent FFR-Driven ATPG with Advanced Circuit Representation Guided Reinforcement Learning25 Nov 2025
- 2025BoolSkeleton: Boolean Network Skeletonization via Homogeneous Pattern Reduction4 Nov 2025
- 2025TRACE: Learning to Compute on Circuit Graphs26 Sep 2025
- 2025Alignment Unlocks Complementarity: A Framework for Multiview Circuit Representation Learning25 Sep 2025
12 newest of 30 All 30 (JSON)