DeepGate: Learning Neural Representations of Logic Gates
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Abstract (arXiv)
Applying deep learning (DL) techniques in the electronic design automation (EDA) field has become a trending topic. Most solutions apply well-developed DL models to solve specific EDA problems. While demonstrating promising results, they require careful model tuning for every problem. The fundamental question on "How to obtain a general and effective neural representation of circuits?" has not been answered yet. In this work, we take the first step towards solving this problem. We propose DeepGate, a novel representation learning solution that effectively embeds both logic function and structural information of a circuit as vectors on each gate. Specifically, we propose transforming circuits into unified and-inverter graph format for learning and using signal probabilities as the supervision task in DeepGate. We then introduce a novel graph neural network that uses strong inductive biases in practical circuits as learning priors for signal probability prediction. Our experimental results show the efficacy and generalization capability of DeepGate.
Key facts. Cited by 37 papers in the map (data through 7 Oct 2026). Builds on 20 of its 32 references that are in the map. First posted on arXiv 26 Nov 2021.
Builds on
20 of 32 references.
References · 20
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Citing papers per year: 2022: 2; 2023: 4; 2024: 8; 2025: 17; 2026: 6.
37 papers.
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- 2023LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automationcited by 40
- 2023DeepGate2: Functionality-Aware Circuit Representation Learningcited by 33
- 2024DeepGate3: Towards Scalable Circuit Representation Learningcited by 26
- 2025DeepCircuitX: A Comprehensive Repository-Level Dataset for RTL Code Understanding, Generation, and PPA Analysiscited by 21
- 2025DeepGate4: Efficient and Effective Representation Learning for Circuit Design at Scalecited by 12
- 2022DeepSAT: An EDA-Driven Learning Framework for SATcited by 11
- 2024Retrieval-Guided Reinforcement Learning for Boolean Circuit Minimizationcited by 10
- 2022TAG: Learning Circuit Spatial Embedding From Layoutscited by 9
- 2025NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graphcited by 9
- 2025Revolution or Hype? Seeking the Limits of Large Models in Hardware Designcited by 9
- 2023DeepSeq: Deep Sequential Circuit Learningcited by 7
- 2025MMCircuitEval: A Comprehensive Multimodal Circuit-Focused Benchmark for Evaluating LLMscited by 6
25 more
- 2024PreRoutGNN for Timing Prediction with Order Preserving Partition: Global Circuit Pre-training, Local Delay Learning and Attentional Cell Modelingcited by 5
- 2024Circuit Transformer: A Transformer That Preserves Logical Equivalencecited by 5
- 2024DeepSeq2: Enhanced Sequential Circuit Learning with Disentangled Representationscited by 5
- 2023Verilog-to-PyG -- A Framework for Graph Learning and Augmentation on RTL Designscited by 4
- 2024OpenLS-DGF: An Adaptive Open-Source Dataset Generation Framework for Machine Learning Tasks in Logic Synthesiscited by 3
- 2025DeepCell: Self-Supervised Multiview Fusion for Circuit Representation Learningcited by 3
- 2025DICE: Device-level Integrated Circuits Encoder with Graph Contrastive Pretrainingcited by 2
- 2024SeaDAG: Semi-autoregressive Diffusion for Conditional Directed Acyclic Graph Generationcited by 1
- 2025GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignmentcited by 1
- 2025FuncGNN: Learning Functional Semantics of Logic Circuits with Graph Neural Networkscited by 1
- 2025Alignment Unlocks Complementarity: A Framework for Multiview Circuit Representation Learningcited by 1
- 2025BDD2Seq: Enabling Scalable Reversible-Circuit Synthesis via Graph-to-Sequence Learningcited by 1
- 2025STELLAR: Structure-guided LLM Assertion Retrieval and Generation for Formal Verificationcited by 1
- 2024SiHGNN: Leveraging Properties of Semantic Graphs for Efficient HGNN Accelerationcited by 0
- 2025Learning Library Cell Representations in Vector Spacecited by 0
- 2025Modeling Relational Logic Circuits for And-Inverter Graph Convolutional Networkcited by 0
- 2025TRACE: Learning to Compute on Circuit Graphscited by 0
- 2025BoolSkeleton: Boolean Network Skeletonization via Homogeneous Pattern Reductioncited by 0
- 2025InF-ATPG: Intelligent FFR-Driven ATPG with Advanced Circuit Representation Guided Reinforcement Learningcited by 0
- 2026GNN-based Path-aware multi-view Circuit Learning for Technology Mappingcited by 0
- 2026KCLNet: Electrically Equivalence-Oriented Graph Representation Learning for Analog Circuitscited by 0
- 2026Graph Computation Meets Circuit Algebra: A Task-Aligned Analysis of Graph Neural Networks for Electronic Design Automationcited by 0
- 2026Beyond Flat Netlist: Hierarchical Graph Representation Learning for Scalable Analysis of Sequential Circuitscited by 0
- 2026LevelSyn: Physical-Aware Logic Synthesis via Level-Asynchronous Graph Neural Networkscited by 0
- 2026ReDIL-GNN: Resynthesis Domain Incremental Learning for Circuit Graph Neural Networkscited by 0
- 2026ReDIL-GNN: Resynthesis Domain Incremental Learning for Circuit Graph Neural Networks16 Sep 2026
- 2026LevelSyn: Physical-Aware Logic Synthesis via Level-Asynchronous Graph Neural Networks3 Sep 2026
- 2026Beyond Flat Netlist: Hierarchical Graph Representation Learning for Scalable Analysis of Sequential Circuits28 Aug 2026
- 2026Graph Computation Meets Circuit Algebra: A Task-Aligned Analysis of Graph Neural Networks for Electronic Design Automation8 May 2026
- 2026KCLNet: Electrically Equivalence-Oriented Graph Representation Learning for Analog Circuits25 Mar 2026
- 2026GNN-based Path-aware multi-view Circuit Learning for Technology Mapping14 Jan 2026
- 2025STELLAR: Structure-guided LLM Assertion Retrieval and Generation for Formal Verification28 Nov 2025
- 2025InF-ATPG: Intelligent FFR-Driven ATPG with Advanced Circuit Representation Guided Reinforcement Learning25 Nov 2025
- 2025BDD2Seq: Enabling Scalable Reversible-Circuit Synthesis via Graph-to-Sequence Learning11 Nov 2025
- 2025BoolSkeleton: Boolean Network Skeletonization via Homogeneous Pattern Reduction4 Nov 2025
- 2025TRACE: Learning to Compute on Circuit Graphs26 Sep 2025
- 2025Alignment Unlocks Complementarity: A Framework for Multiview Circuit Representation Learning25 Sep 2025
25 more
- 2025Revolution or Hype? Seeking the Limits of Large Models in Hardware Design5 Sep 2025
- 2025Modeling Relational Logic Circuits for And-Inverter Graph Convolutional Network16 Aug 2025
- 2025MMCircuitEval: A Comprehensive Multimodal Circuit-Focused Benchmark for Evaluating LLMs20 Jul 2025
- 2025FuncGNN: Learning Functional Semantics of Logic Circuits with Graph Neural Networks7 Jun 2025
- 2025GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignment13 Apr 2025
- 2025NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph12 Apr 2025
- 2025Learning Library Cell Representations in Vector Space28 Mar 2025
- 2025DeepCircuitX: A Comprehensive Repository-Level Dataset for RTL Code Understanding, Generation, and PPA Analysis25 Feb 2025
- 2025DICE: Device-level Integrated Circuits Encoder with Graph Contrastive Pretraining13 Feb 2025
- 2025DeepCell: Self-Supervised Multiview Fusion for Circuit Representation Learning5 Feb 2025
- 2025DeepGate4: Efficient and Effective Representation Learning for Circuit Design at Scale2 Feb 2025
- 2024OpenLS-DGF: An Adaptive Open-Source Dataset Generation Framework for Machine Learning Tasks in Logic Synthesis14 Nov 2024
- 2024DeepSeq2: Enhanced Sequential Circuit Learning with Disentangled Representations1 Nov 2024
- 2024SeaDAG: Semi-autoregressive Diffusion for Conditional Directed Acyclic Graph Generation21 Oct 2024
- 2024SiHGNN: Leveraging Properties of Semantic Graphs for Efficient HGNN Acceleration27 Aug 2024
- 2024DeepGate3: Towards Scalable Circuit Representation Learning15 Jul 2024
- 2024Circuit Transformer: A Transformer That Preserves Logical Equivalence14 Mar 2024
- 2024PreRoutGNN for Timing Prediction with Order Preserving Partition: Global Circuit Pre-training, Local Delay Learning and Attentional Cell Modeling27 Feb 2024
- 2024Retrieval-Guided Reinforcement Learning for Boolean Circuit Minimization22 Jan 2024
- 2023LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automation28 Dec 2023
- 2023Verilog-to-PyG -- A Framework for Graph Learning and Augmentation on RTL Designs9 Nov 2023
- 2023DeepGate2: Functionality-Aware Circuit Representation Learning25 May 2023
- 2023DeepSeq: Deep Sequential Circuit Learning27 Feb 2023
- 2022TAG: Learning Circuit Spatial Embedding From Layouts7 Sep 2022
- 2022DeepSAT: An EDA-Driven Learning Framework for SAT27 May 2022
- 2023LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automationcited by 40
- 2023DeepGate2: Functionality-Aware Circuit Representation Learningcited by 33
- 2024DeepGate3: Towards Scalable Circuit Representation Learningcited by 26
- 2025DeepCircuitX: A Comprehensive Repository-Level Dataset for RTL Code Understanding, Generation, and PPA Analysiscited by 21
- 2025DeepGate4: Efficient and Effective Representation Learning for Circuit Design at Scalecited by 12
- 2022DeepSAT: An EDA-Driven Learning Framework for SATcited by 11
- 2024Retrieval-Guided Reinforcement Learning for Boolean Circuit Minimizationcited by 10
- 2022TAG: Learning Circuit Spatial Embedding From Layoutscited by 9
- 2025NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graphcited by 9
- 2025Revolution or Hype? Seeking the Limits of Large Models in Hardware Designcited by 9
- 2023DeepSeq: Deep Sequential Circuit Learningcited by 7
- 2024PreRoutGNN for Timing Prediction with Order Preserving Partition: Global Circuit Pre-training, Local Delay Learning and Attentional Cell Modelingcited by 5
12 most cited of 34 All 34 (JSON)
- 2026ReDIL-GNN: Resynthesis Domain Incremental Learning for Circuit Graph Neural Networks16 Sep 2026
- 2026LevelSyn: Physical-Aware Logic Synthesis via Level-Asynchronous Graph Neural Networks3 Sep 2026
- 2026Beyond Flat Netlist: Hierarchical Graph Representation Learning for Scalable Analysis of Sequential Circuits28 Aug 2026
- 2026Graph Computation Meets Circuit Algebra: A Task-Aligned Analysis of Graph Neural Networks for Electronic Design Automation8 May 2026
- 2026KCLNet: Electrically Equivalence-Oriented Graph Representation Learning for Analog Circuits25 Mar 2026
- 2026GNN-based Path-aware multi-view Circuit Learning for Technology Mapping14 Jan 2026
- 2025STELLAR: Structure-guided LLM Assertion Retrieval and Generation for Formal Verification28 Nov 2025
- 2025InF-ATPG: Intelligent FFR-Driven ATPG with Advanced Circuit Representation Guided Reinforcement Learning25 Nov 2025
- 2025BDD2Seq: Enabling Scalable Reversible-Circuit Synthesis via Graph-to-Sequence Learning11 Nov 2025
- 2025BoolSkeleton: Boolean Network Skeletonization via Homogeneous Pattern Reduction4 Nov 2025
- 2025TRACE: Learning to Compute on Circuit Graphs26 Sep 2025
- 2025Alignment Unlocks Complementarity: A Framework for Multiview Circuit Representation Learning25 Sep 2025
12 newest of 34 All 34 (JSON)