mlsanityData to 7 Oct 2026

(Security) Assertions by Large Language Models

arXiv 2306.14027 ↗First posted 24 Jun 2023cs.CR cs.AIcited by 31

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Abstract (arXiv)

The security of computer systems typically relies on a hardware root of trust. As vulnerabilities in hardware can have severe implications on a system, there is a need for techniques to support security verification activities. Assertion-based verification is a popular verification technique that involves capturing design intent in a set of assertions that can be used in formal verification or testing-based checking. However, writing security-centric assertions is a challenging task. In this work, we investigate the use of emerging large language models (LLMs) for code generation in hardware assertion generation for security, where primarily natural language prompts, such as those one would see as code comments in assertion files, are used to produce SystemVerilog assertions. We focus our attention on a popular LLM and characterize its ability to write assertions out of the box, given varying levels of detail in the prompt. We design an evaluation framework that generates a variety of prompts, and we create a benchmark suite comprising real-world hardware designs and corresponding golden reference assertions that we want to generate with the LLM.

Key facts. Cited by 31 papers in the map (data through 7 Oct 2026). Builds on 13 of its 67 references that are in the map. First posted on arXiv 24 Jun 2023.

Builds on

13 of 67 references.

References · 13

  1. 2017Attention Is All You Needcited by 59,932
  2. 2018BERT: Pre-training of Deep Bidirectional Transformers for Language Understandingcited by 40,204
  3. 2021Evaluating Large Language Models Trained on Codecited by 8,053
  4. 2019Megatron-LM: Training Multi-Billion Parameter Language Models Using Model Parallelismcited by 1,829
  5. 2022CodeGen: An Open Large Language Model for Code with Multi-Turn Program Synthesiscited by 876
  6. 2021Asleep at the Keyboard? Assessing the Security of GitHub Copilot's Code Contributionscited by 417
  7. 2022Benchmarking Large Language Models for Automated Verilog RTL Code Generationcited by 112
  8. 2020DAVE: Deriving Automatically Verilog from Englishcited by 46
  9. 2021Fuzzing Hardware Like Softwarecited by 9
  10. 2022TheHuzz: Instruction Fuzzing of Processors Using Golden-Reference Models for Finding Software-Exploitable Vulnerabilitiescited by 5
  11. 2023HyPFuzz: Formal-Assisted Processor Fuzzingcited by 3
  12. 2021The Unpatchable Silicon: A Full Break of the Bitstream Encryption of Xilinx 7-Series FPGAscited by 2
1 more
  1. 2022Neural Program Repair: Systems, Challenges and Solutionscited by 2

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Cited by year (2026 to 7 Oct)

Citing papers per year: 2023: 3; 2024: 9; 2025: 10; 2026: 9.

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  1. 2024Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTScited by 42
  2. 2023LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automationcited by 40
  3. 2024LLM4SecHW: Leveraging Domain Specific Large Language Model for Hardware Debuggingcited by 18
  4. 2024LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trustcited by 18
  5. 2024Automatically Improving LLM-based Verilog Generation using EDA Tool Feedbackcited by 18
  6. 2024AssertionBench: A Benchmark to Evaluate Large-Language Models for Assertion Generationcited by 16
  7. 2025AssertionForge: Enhancing Formal Verification Assertion Generation with Structured Representation of Specifications and RTLcited by 13
  8. 2024Hardware Phi-1.5B: A Large Language Model Encodes Hardware Domain Specific Knowledgecited by 10
  9. 2025Enhancing Large Language Models for Hardware Verification: A Novel SystemVerilog Assertion Datasetcited by 10
  10. 2024Evaluating LLMs for Hardware Design and Testcited by 8
  11. 2025Vulnerability Detection: From Formal Verification to Large Language Models and Hybrid Approaches: A Comprehensive Overviewcited by 7
  12. 2025ThreatLens: LLM-guided Threat Modeling and Test Plan Generation for Hardware Security Verificationcited by 7
19 more
  1. 2023ZeroLeak: Using LLMs for Scalable and Cost Effective Side-Channel Patchingcited by 6
  2. 2025SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Modelscited by 5
  3. 2026ChatSVA: Bridging SVA Generation for Hardware Verification via Task-Specific LLMscited by 5
  4. 2025Towards LLM-based Root Cause Analysis of Hardware Design Failurescited by 4
  5. 2024LLM-aided explanations of EDA synthesis errorscited by 3
  6. 2024Automatic High-quality Verilog Assertion Generation through Subtask-Focused Fine-Tuned LLMs and Iterative Promptingcited by 3
  7. 2025SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refinecited by 2
  8. 2026QiMeng-CodeV-SVA: Training Specialized LLMs for Hardware Assertion Generation via RTL-Grounded Bidirectional Data Synthesiscited by 2
  9. 2026Knowledge Graphs, the Missing Link in Agentic AI-based Formal Verificationcited by 2
  10. 2023Towards Auto-Modeling of Formal Verification for NextG Protocols: A Multimodal cross- and self-attention Large Language Model Approachcited by 1
  11. 2025Overcoming Vision Language Model Challenges in Diagram Understanding: A Proof-of-Concept with XML-Driven Large Language Models Solutionscited by 1
  12. 2025GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignmentcited by 1
  13. 2025CUFG: Curriculum Unlearning Guided by the Forgetting Gradientcited by 1
  14. 2026GUIDE: GenAI Units In Digital Design Educationcited by 1
  15. 2026LLMs for Secure Hardware Design and Related Problems: Opportunities and Challengescited by 1
  16. 2026Robustness of LLM-Generated SystemVerilog Assertions to Semantics-Preserving RTL Transformationscited by 1
  17. 2026FVRuleLearner: Operator-Level Reasoning Tree (Op-Tree)-Based Rules Learning for Formal Verificationcited by 0
  18. 2026Hardware Design and Security in the Era of Chiplets and LLMscited by 0
  19. 2026Trust, but Validate the Instrument: Auditing AI-Generated RTL Verification Plans on Authored Security-Regression Proxiescited by 0