mlsanityData to 14 Oct 2026

Deep Representation Learning for Electronic Design Automation

arXiv 2505.02105 ↗First posted 4 May 2025cs.LGcited by 0

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Abstract (arXiv)

Representation learning has become an effective technique utilized by electronic design automation (EDA) algorithms, which leverage the natural representation of workflow elements as images, grids, and graphs. By addressing challenges related to the increasing complexity of circuits and stringent power, performance, and area (PPA) requirements, representation learning facilitates the automatic extraction of meaningful features from complex data formats, including images, grids, and graphs. This paper examines the application of representation learning in EDA, covering foundational concepts and analyzing prior work and case studies on tasks that include timing prediction, routability analysis, and automated placement. Key techniques, including image-based methods, graph-based approaches, and hybrid multimodal solutions, are presented to illustrate the improvements provided in routing, timing, and parasitic prediction. The provided advancements demonstrate the potential of representation learning to enhance efficiency, accuracy, and scalability in current integrated circuit design flows.

Key facts. No citing papers in the map yet (data through 14 Oct 2026). Builds on 19 of its 61 references that are in the map. First posted on arXiv 4 May 2025.

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19 of 61 references.

References · 19

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7 more
  1. 2021Machine Learning for Electronic Design Automation: A Surveycited by 72
  2. 2023LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automationcited by 40
  3. 2021Few-shot Knowledge Graph-to-Text Generation with Pretrained Language Modelscited by 29
  4. 2024Evaluating LLMs for Hardware Design and Testcited by 8
  5. 2024LLM-aided explanations of EDA synthesis errorscited by 3
  6. 2024RoutePlacer: An End-to-End Routability-Aware Placer with Graph Neural Networkcited by 1
  7. 2024Non-Overlapping Placement of Macro Cells based on Reinforcement Learning in Chip Designcited by 1

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