mlsanityData to 7 Oct 2026

QiMeng-CodeV-SVA: Training Specialized LLMs for Hardware Assertion Generation via RTL-Grounded Bidirectional Data Synthesis

arXiv 2603.14239 ↗First posted 15 Mar 2026cs.CL cs.AI cs.ARcited by 2

On the map: Synthetic data and self-improvement for LLMs → Code and instruction data synthesis

Abstract (arXiv)

SystemVerilog Assertions (SVAs) are crucial for hardware verification. Recent studies leverage general-purpose LLMs to translate natural language properties to SVAs (NL2SVA), but they perform poorly due to limited data. We propose a data synthesis framework to tackle two challenges: the scarcity of high-quality real-world SVA corpora and the lack of reliable methods to determine NL-SVA semantic equivalence. For the former, large-scale open-source RTLs are used to guide LLMs to generate real-world SVAs; for the latter, bidirectional translation serves as a data selection method. With the synthesized data, we train CodeV-SVA, a series of SVA generation models. Notably, CodeV-SVA-14B achieves 75.8% on NL2SVA-Human and 84.0% on NL2SVA-Machine in Func.@1, matching or exceeding advanced LLMs like GPT-5 and DeepSeek-R1.

Key facts. Cited by 2 papers in the map (data through 7 Oct 2026). Placed in Code and instruction data synthesis, one of 13 directions in Synthetic data and self-improvement for LLMs. Builds on 20 of its 36 references that are in the map. First posted on arXiv 15 Mar 2026.

Builds on

20 of 36 references.

References · 20

  1. 2020Language Models are Few-Shot Learnerscited by 32,199
  2. 2021Evaluating Large Language Models Trained on Codecited by 8,053
  3. 2024A Survey on LLM-as-a-Judgecited by 1,384
  4. 2024A Survey on Data Selection for LLM Instruction Tuningcited by 76
  5. 2023LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automationcited by 40
  6. 2024AutoBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Designcited by 38
  7. 2025QiMeng-CodeV-R1: Reasoning-Enhanced Verilog Generationcited by 34
  8. 2023(Security) Assertions by Large Language Modelscited by 31
  9. 2024AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMscited by 30
  10. 2024CorrectBench: Automatic Testbench Generation with Functional Self-Correction using LLMs for HDL Designcited by 23
  11. 2025DeepCircuitX: A Comprehensive Repository-Level Dataset for RTL Code Understanding, Generation, and PPA Analysiscited by 21
  12. 2024UVLLM: An Automated Universal RTL Verification Framework using LLMscited by 17
8 more
  1. 2025AssertionForge: Enhancing Formal Verification Assertion Generation with Structured Representation of Specifications and RTLcited by 13
  2. 2024FVEval: Understanding Language Model Capabilities in Formal Verification of Digital Hardwarecited by 9
  3. 2025From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verificationcited by 8
  4. 2025Hybrid-NL2SVA: Integrating RAG and Finetuning for LLM-based NL2SVAcited by 5
  5. 2025AssertGen: Enhancement of LLM-aided Assertion Generation through Cross-Layer Signal Bridgingcited by 4
  6. 2025FVDebug: An LLM-Driven Debugging Assistant for Automated Root Cause Analysis of Formal Verification Failurescited by 4
  7. 2025AssertFix: Empowering Automated Assertion Fix via Large Language Modelscited by 2
  8. 2025DeepAssert: An LLM-Aided Verification Framework with Fine-Grained Assertion Generation for Modules with Extracted Module Specificationscited by 1

Built on by

Cited by year (2026 to 7 Oct)

Citing papers per year: 2026: 2.

2 papers.

  1. 2026Reward-Weighted On-Policy Distillation with an Open Property-Equivalence Verifier for NL-to-SVA Generationcited by 3
  2. 2026BEHAVE: Functional Behavior Modeling Enables Self-Improving Agents for Hardware Design and Verificationcited by 0

Similar, not cited

Close in wording, no citation either way

  1. 2026From Language to Logic: Bridging LLMs & Formal Representations for RTL Assertion Generation
  2. 2025AssertCoder: LLM-Based Assertion Generation via Multimodal Specification Extraction
  3. 2026SpecAlign: A Semantic Alignment Framework for SystemVerilog Assertion Generation
  4. 2026HierSVA: A Data Synthesis Pipeline, Dataset, and Benchmark for LLM-Driven Hierarchical Hardware Formal Verification
  5. 2025SysVCoder: An LLM-Driven Framework for Systematic Generation of System-Level Design
  6. 2025SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine
  7. 2025Large Language Model for Verilog Code Generation: Literature Review and the Road Ahead
  8. 2024MetRex: A Benchmark for Verilog Code Metric Reasoning Using LLMs