DRiLLS: Deep Reinforcement Learning for Logic Synthesis
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Abstract (arXiv)
Logic synthesis requires extensive tuning of the synthesis optimization flow where the quality of results (QoR) depends on the sequence of optimizations used. Efficient design space exploration is challenging due to the exponential number of possible optimization permutations. Therefore, automating the optimization process is necessary. In this work, we propose a novel reinforcement learning-based methodology that navigates the optimization space without human intervention. We demonstrate the training of an Advantage Actor Critic (A2C) agent that seeks to minimize area subject to a timing constraint. Using the proposed methodology, designs can be optimized autonomously with no-humans in-loop. Evaluation on the comprehensive EPFL benchmark suite shows that the agent outperforms existing exploration methodologies and improves QoRs by an average of 13%.
Key facts. Cited by 47 papers in the map (data through 7 Oct 2026). First posted on arXiv 11 Nov 2019.
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Citing papers per year: 2021: 5; 2022: 12; 2023: 9; 2024: 13; 2025: 5; 2026: 3.
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- 2021Machine Learning for Electronic Design Automation: A Surveycited by 71
- 2021A Survey of Machine Learning for Computer Architecture and Systemscited by 53
- 2023LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automationcited by 40
- 2021OpenABC-D: A Large-Scale Dataset For Machine Learning Guided Integrated Circuit Synthesiscited by 30
- 2021BOiLS: Bayesian Optimisation for Logic Synthesiscited by 18
- 2023Advanced Large Language Model (LLM)-Driven Verilog Development: Enhancing Power, Performance, and Area Optimization in Code Synthesiscited by 14
- 2022Pretraining Graph Neural Networks for few-shot Analog Circuit Modeling and Designcited by 13
- 2022DevFormer: A Symmetric Transformer for Context-Aware Device Placementcited by 11
- 2022DeepTPI: Test Point Insertion with Deep Reinforcement Learningcited by 10
- 2024Retrieval-Guided Reinforcement Learning for Boolean Circuit Minimizationcited by 10
- 2024Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designscited by 9
- 2022LOSTIN: Logic Optimization via Spatio-Temporal Information with Hybrid Graph Modelscited by 7
35 more
- 2023A Circuit Domain Generalization Framework for Efficient Logic Synthesis in Chip Designcited by 6
- 2024Circuit Transformer: A Transformer That Preserves Logical Equivalencecited by 5
- 2025LLM-VeriPPA: Power, Performance, and Area Optimization aware Verilog Code Generation with Large Language Modelscited by 5
- 2023AISYN: AI-driven Reinforcement Learning-Based Logic Synthesis Frameworkcited by 4
- 2024Logic Synthesis with Generative Deep Neural Networkscited by 4
- 2024MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuningcited by 4
- 2022Reinforcement Learning for Hardware Security: Opportunities, Developments, and Challengescited by 3
- 2023INVICTUS: Optimizing Boolean Logic Circuit Synthesis via Synergistic Learning and Searchcited by 3
- 2024OpenLS-DGF: An Adaptive Open-Source Dataset Generation Framework for Machine Learning Tasks in Logic Synthesiscited by 3
- 2025VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Codecited by 3
- 2022Rethinking Reinforcement Learning based Logic Synthesiscited by 2
- 2023Adaptive Reconvergence-driven AIG Rewriting via Strategy Learningcited by 2
- 2024BoolGebra: Attributed Graph-learning for Boolean Algebraic Manipulationcited by 2
- 2024ShortCircuit: AlphaZero-Driven Circuit Designcited by 2
- 2024MTLSO: A Multi-Task Learning Approach for Logic Synthesis Optimizationcited by 2
- 2022Too Big to Fail? Active Few-Shot Learning Guided Logic Synthesiscited by 1
- 2022HybMT: Hybrid Meta-Predictor based ML Algorithm for Fast Test Vector Generationcited by 1
- 2022The prediction of the quality of results in Logic Synthesis using Transformer and Graph Neural Networkscited by 1
- 2022Neural Combinatorial Logic Circuit Synthesis from Input-Output Examplescited by 1
- 2023Towards the Imagenets of ML4EDAcited by 1
- 2024Logic Synthesis Optimization with Predictive Self-Supervision via Causal Transformerscited by 1
- 2024Boolean-aware Boolean Circuit Classification: A Comprehensive Study on Graph Neural Networkcited by 1
- 2025Graph Neural Networks for Automatic Addition of Optimizing Components in Printed Circuit Board Schematicscited by 1
- 2026Report for NSF Workshop on AI for Electronic Design Automationcited by 1
- 2021Reinforcement Learning for Scalable Logic Optimization with Graph Neural Networkscited by 0
- 2022The Dark Side: Security Concerns in Machine Learning for EDAcited by 0
- 2022Intelligent Circuit Design and Implementation with Machine Learningcited by 0
- 2023Statistical Hardware Design With Multi-model Active Learningcited by 0
- 2023GraPhSyM: Graph Physical Synthesis Modelcited by 0
- 2024An Open-source End-to-End Logic Optimization Framework for Large-scale Boolean Network with Reinforcement Learningcited by 0
- 2024ASCENT: Amplifying Power Side-Channel Resilience via Learning & Monte-Carlo Tree Searchcited by 0
- 2025QiMeng: Fully Automated Hardware and Software Design for Processor Chipcited by 0
- 2025GENIAL: Generative Design Space Exploration via Network Inversion for Low Power Algorithmic Logic Unitscited by 0
- 2026SynAct: A Reasoning-Acting Large Language Model Agent for Adaptive Synthesis Optimizationcited by 0
- 2026SKILL: Self-correcting Knowledge-guided Iterative Large Language Model Agent for Logic Optimizationcited by 0
- 2026SynAct: A Reasoning-Acting Large Language Model Agent for Adaptive Synthesis Optimization13 Aug 2026
- 2026SKILL: Self-correcting Knowledge-guided Iterative Large Language Model Agent for Logic Optimization12 Jun 2026
- 2026Report for NSF Workshop on AI for Electronic Design Automation20 Jan 2026
- 2025LLM-VeriPPA: Power, Performance, and Area Optimization aware Verilog Code Generation with Large Language Models10 Sep 2025
- 2025GENIAL: Generative Design Space Exploration via Network Inversion for Low Power Algorithmic Logic Units25 Jul 2025
- 2025Graph Neural Networks for Automatic Addition of Optimizing Components in Printed Circuit Board Schematics12 Jun 2025
- 2025VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code8 Jun 2025
- 2025QiMeng: Fully Automated Hardware and Software Design for Processor Chip5 Jun 2025
- 2024OpenLS-DGF: An Adaptive Open-Source Dataset Generation Framework for Machine Learning Tasks in Logic Synthesis14 Nov 2024
- 2024Boolean-aware Boolean Circuit Classification: A Comprehensive Study on Graph Neural Network13 Nov 2024
- 2024Logic Synthesis Optimization with Predictive Self-Supervision via Causal Transformers16 Sep 2024
- 2024MTLSO: A Multi-Task Learning Approach for Logic Synthesis Optimization9 Sep 2024
35 more
- 2024ShortCircuit: AlphaZero-Driven Circuit Design19 Aug 2024
- 2024MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning25 Jul 2024
- 2024ASCENT: Amplifying Power Side-Channel Resilience via Learning & Monte-Carlo Tree Search27 Jun 2024
- 2024Logic Synthesis with Generative Deep Neural Networks7 Jun 2024
- 2024Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs10 May 2024
- 2024An Open-source End-to-End Logic Optimization Framework for Large-scale Boolean Network with Reinforcement Learning26 Mar 2024
- 2024Circuit Transformer: A Transformer That Preserves Logical Equivalence14 Mar 2024
- 2024Retrieval-Guided Reinforcement Learning for Boolean Circuit Minimization22 Jan 2024
- 2024BoolGebra: Attributed Graph-learning for Boolean Algebraic Manipulation19 Jan 2024
- 2023LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automation28 Dec 2023
- 2023Adaptive Reconvergence-driven AIG Rewriting via Strategy Learning22 Dec 2023
- 2023Advanced Large Language Model (LLM)-Driven Verilog Development: Enhancing Power, Performance, and Area Optimization in Code Synthesis2 Dec 2023
- 2023Towards the Imagenets of ML4EDA16 Oct 2023
- 2023A Circuit Domain Generalization Framework for Efficient Logic Synthesis in Chip Design22 Aug 2023
- 2023GraPhSyM: Graph Physical Synthesis Model7 Aug 2023
- 2023INVICTUS: Optimizing Boolean Logic Circuit Synthesis via Synergistic Learning and Search22 May 2023
- 2023Statistical Hardware Design With Multi-model Active Learning14 Mar 2023
- 2023AISYN: AI-driven Reinforcement Learning-Based Logic Synthesis Framework8 Feb 2023
- 2022Neural Combinatorial Logic Circuit Synthesis from Input-Output Examples29 Oct 2022
- 2022Reinforcement Learning for Hardware Security: Opportunities, Developments, and Challenges29 Aug 2022
- 2022The prediction of the quality of results in Logic Synthesis using Transformer and Graph Neural Networks23 Jul 2022
- 2022HybMT: Hybrid Meta-Predictor based ML Algorithm for Fast Test Vector Generation22 Jul 2022
- 2022DeepTPI: Test Point Insertion with Deep Reinforcement Learning7 Jun 2022
- 2022Intelligent Circuit Design and Implementation with Machine Learning7 Jun 2022
- 2022DevFormer: A Symmetric Transformer for Context-Aware Device Placement26 May 2022
- 2022Rethinking Reinforcement Learning based Logic Synthesis16 May 2022
- 2022Too Big to Fail? Active Few-Shot Learning Guided Logic Synthesis5 Apr 2022
- 2022Pretraining Graph Neural Networks for few-shot Analog Circuit Modeling and Design29 Mar 2022
- 2022The Dark Side: Security Concerns in Machine Learning for EDA20 Mar 2022
- 2022LOSTIN: Logic Optimization via Spatio-Temporal Information with Hybrid Graph Models20 Jan 2022
- 2021BOiLS: Bayesian Optimisation for Logic Synthesis11 Nov 2021
- 2021OpenABC-D: A Large-Scale Dataset For Machine Learning Guided Integrated Circuit Synthesis21 Oct 2021
- 2021Reinforcement Learning for Scalable Logic Optimization with Graph Neural Networks4 May 2021
- 2021A Survey of Machine Learning for Computer Architecture and Systems16 Feb 2021
- 2021Machine Learning for Electronic Design Automation: A Survey10 Jan 2021
- 2021Machine Learning for Electronic Design Automation: A Surveycited by 71
- 2021A Survey of Machine Learning for Computer Architecture and Systemscited by 53
- 2023LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automationcited by 40
- 2021OpenABC-D: A Large-Scale Dataset For Machine Learning Guided Integrated Circuit Synthesiscited by 30
- 2021BOiLS: Bayesian Optimisation for Logic Synthesiscited by 18
- 2023Advanced Large Language Model (LLM)-Driven Verilog Development: Enhancing Power, Performance, and Area Optimization in Code Synthesiscited by 14
- 2022Pretraining Graph Neural Networks for few-shot Analog Circuit Modeling and Designcited by 13
- 2022DevFormer: A Symmetric Transformer for Context-Aware Device Placementcited by 11
- 2022DeepTPI: Test Point Insertion with Deep Reinforcement Learningcited by 10
- 2024Retrieval-Guided Reinforcement Learning for Boolean Circuit Minimizationcited by 10
- 2024Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designscited by 9
- 2022LOSTIN: Logic Optimization via Spatio-Temporal Information with Hybrid Graph Modelscited by 7
12 most cited of 45 All 45 (JSON)
- 2026Report for NSF Workshop on AI for Electronic Design Automation20 Jan 2026
- 2025LLM-VeriPPA: Power, Performance, and Area Optimization aware Verilog Code Generation with Large Language Models10 Sep 2025
- 2025GENIAL: Generative Design Space Exploration via Network Inversion for Low Power Algorithmic Logic Units25 Jul 2025
- 2025Graph Neural Networks for Automatic Addition of Optimizing Components in Printed Circuit Board Schematics12 Jun 2025
- 2025VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code8 Jun 2025
- 2025QiMeng: Fully Automated Hardware and Software Design for Processor Chip5 Jun 2025
- 2024OpenLS-DGF: An Adaptive Open-Source Dataset Generation Framework for Machine Learning Tasks in Logic Synthesis14 Nov 2024
- 2024Boolean-aware Boolean Circuit Classification: A Comprehensive Study on Graph Neural Network13 Nov 2024
- 2024Logic Synthesis Optimization with Predictive Self-Supervision via Causal Transformers16 Sep 2024
- 2024MTLSO: A Multi-Task Learning Approach for Logic Synthesis Optimization9 Sep 2024
- 2024ShortCircuit: AlphaZero-Driven Circuit Design19 Aug 2024
- 2024MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning25 Jul 2024
12 newest of 45 All 45 (JSON)