OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation
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Abstract (arXiv)
The automated generation of design RTL based on large language model (LLM) and natural language instructions has demonstrated great potential in agile circuit design. However, the lack of datasets and benchmarks in the public domain prevents the development and fair evaluation of LLM solutions. This paper highlights our latest advances in open datasets and benchmarks from three perspectives: (1) RTLLM 2.0, an updated benchmark assessing LLM's capability in design RTL generation. The benchmark is augmented to 50 hand-crafted designs. Each design provides the design description, test cases, and a correct RTL code. (2) AssertEval, an open-source benchmark assessing the LLM's assertion generation capabilities for RTL verification. The benchmark includes 18 designs, each providing specification, signal definition, and correct RTL code. (3) RTLCoder-Data, an extended open-source dataset with 80K instruction-code data samples. Moreover, we propose a new verification-based method to verify the functionality correctness of training data samples. Based on this technique, we further release a dataset with 7K verified high-quality samples. These three studies are integrated into one framework, providing off-the-shelf support for the development and evaluation of LLMs for RTL code generation and verification. Finally, extensive experiments indicate that LLM performance can be boosted by enlarging the training dataset, improving data quality, and improving the training scheme.
Key facts. Cited by 30 papers in the map (data through 7 Oct 2026). First posted on arXiv 19 Mar 2025.
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Citing papers per year: 2025: 15; 2026: 15.
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- 2025Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verificationcited by 41
- 2025VeriMoA: A Mixture-of-Agents Framework for Spec-to-HDL Generationcited by 15
- 2025Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedbackcited by 14
- 2025RealBench: Benchmarking Verilog Generation Models with Real-World IP Designscited by 14
- 2025ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Modelcited by 12
- 2025VeriCoder: Enhancing LLM-Based RTL Code Generation through Functional Correctness Validationcited by 11
- 2025VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generationcited by 8
- 2025Large Language Model for Verilog Code Generation: Literature Review and the Road Aheadcited by 7
- 2026EvolVE: Evolutionary Search for LLM-based Verilog Generation and Optimizationcited by 7
- 2026ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Designcited by 7
- 2025MMCircuitEval: A Comprehensive Multimodal Circuit-Focused Benchmark for Evaluating LLMscited by 6
- 2026Agentic Hardware Design as Repository-Level Code Evolutioncited by 6
18 more
- 2025ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflectioncited by 5
- 2025QiMeng-SALV: Signal-Aware Learning for Verilog Code Generationcited by 4
- 2025REvolution: An Evolutionary Framework for RTL Generation driven by Large Language Modelscited by 4
- 2026SiliconMind-V1: Multi-Agent Distillation and Debug-Reasoning Workflows for Verilog Code Generationcited by 4
- 2025Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMscited by 2
- 2025EvoVerilog: Large Langugage Model Assisted Evolution of Verilog Codecited by 2
- 2025DeepV: A Model-Agnostic Retrieval-Augmented Framework for Verilog Code Generation with a High-Quality Knowledge Basecited by 1
- 2026Configuration Over Selection: Hyperparameter Sensitivity Exceeds Model Differences in Open-Source LLMs for RTL Generationcited by 1
- 2026ChipMATE: Multi-Agent Training via Reinforcement Learning for Enhanced RTL Generationcited by 1
- 2026Alpha-RTL: Test-Time Training for RTL Hardware Optimizationcited by 1
- 2026AutoPPA: Automated Circuit PPA Optimization via Contrastive Code-based Rule Library Learningcited by 0
- 2026LEGO: An LLM Skill-Based Front-End Design Generation Platformcited by 0
- 2026From Mirage to Grounding: Towards Reliable Multimodal Circuit-to-Verilog Code Generationcited by 0
- 2026HierSVA: A Data Synthesis Pipeline, Dataset, and Benchmark for LLM-Driven Hierarchical Hardware Formal Verificationcited by 0
- 2026Agentic Electronic Design Automation: A Handoff Perspectivecited by 0
- 2026RTLCurator: Label-Efficient Data Curation for RTL Generationcited by 0
- 2026PerfReasoning: How Well Do LLMs Reason on Hardware Performance?cited by 0
- 2026TicTacBench: Benchmarking Timing Closure Capabilities of Coding Agentscited by 0
- 2026TicTacBench: Benchmarking Timing Closure Capabilities of Coding Agents20 Sep 2026
- 2026PerfReasoning: How Well Do LLMs Reason on Hardware Performance?3 Sep 2026
- 2026RTLCurator: Label-Efficient Data Curation for RTL Generation31 Jul 2026
- 2026Agentic Hardware Design as Repository-Level Code Evolution26 Jun 2026
- 2026Agentic Electronic Design Automation: A Handoff Perspective18 Jun 2026
- 2026HierSVA: A Data Synthesis Pipeline, Dataset, and Benchmark for LLM-Driven Hierarchical Hardware Formal Verification9 Jun 2026
- 2026Alpha-RTL: Test-Time Training for RTL Hardware Optimization3 Jun 2026
- 2026ChipMATE: Multi-Agent Training via Reinforcement Learning for Enhanced RTL Generation13 May 2026
- 2026From Mirage to Grounding: Towards Reliable Multimodal Circuit-to-Verilog Code Generation30 Apr 2026
- 2026LEGO: An LLM Skill-Based Front-End Design Generation Platform25 Apr 2026
- 2026AutoPPA: Automated Circuit PPA Optimization via Contrastive Code-based Rule Library Learning20 Apr 2026
- 2026Configuration Over Selection: Hyperparameter Sensitivity Exceeds Model Differences in Open-Source LLMs for RTL Generation18 Apr 2026
18 more
- 2026SiliconMind-V1: Multi-Agent Distillation and Debug-Reasoning Workflows for Verilog Code Generation10 Feb 2026
- 2026ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Design29 Jan 2026
- 2026EvolVE: Evolutionary Search for LLM-based Verilog Generation and Optimization26 Jan 2026
- 2025VeriMoA: A Mixture-of-Agents Framework for Spec-to-HDL Generation31 Oct 2025
- 2025Large Language Model for Verilog Code Generation: Literature Review and the Road Ahead29 Oct 2025
- 2025REvolution: An Evolutionary Framework for RTL Generation driven by Large Language Models24 Oct 2025
- 2025QiMeng-SALV: Signal-Aware Learning for Verilog Code Generation22 Oct 2025
- 2025DeepV: A Model-Agnostic Retrieval-Augmented Framework for Verilog Code Generation with a High-Quality Knowledge Base6 Oct 2025
- 2025RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs22 Jul 2025
- 2025MMCircuitEval: A Comprehensive Multimodal Circuit-Focused Benchmark for Evaluating LLMs20 Jul 2025
- 2025VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation9 Jul 2025
- 2025EvoVerilog: Large Langugage Model Assisted Evolution of Verilog Code26 Jun 2025
- 2025Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification17 Jun 2025
- 2025ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection26 May 2025
- 2025Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs9 May 2025
- 2025Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedback22 Apr 2025
- 2025VeriCoder: Enhancing LLM-Based RTL Code Generation through Functional Correctness Validation22 Apr 2025
- 2025ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model20 Apr 2025
- 2025Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verificationcited by 41
- 2025VeriMoA: A Mixture-of-Agents Framework for Spec-to-HDL Generationcited by 15
- 2026Agentic Hardware Design as Repository-Level Code Evolutioncited by 6
- 2026ChipMATE: Multi-Agent Training via Reinforcement Learning for Enhanced RTL Generationcited by 1
- 2026Agentic Electronic Design Automation: A Handoff Perspectivecited by 0
- 2026TicTacBench: Benchmarking Timing Closure Capabilities of Coding Agentscited by 0
- 2026TicTacBench: Benchmarking Timing Closure Capabilities of Coding Agents20 Sep 2026
- 2026Agentic Hardware Design as Repository-Level Code Evolution26 Jun 2026
- 2026Agentic Electronic Design Automation: A Handoff Perspective18 Jun 2026
- 2026ChipMATE: Multi-Agent Training via Reinforcement Learning for Enhanced RTL Generation13 May 2026
- 2025VeriMoA: A Mixture-of-Agents Framework for Spec-to-HDL Generation31 Oct 2025
- 2025Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification17 Jun 2025
- 2025RealBench: Benchmarking Verilog Generation Models with Real-World IP Designscited by 14
- 2025VeriCoder: Enhancing LLM-Based RTL Code Generation through Functional Correctness Validationcited by 11
- 2025VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generationcited by 8
- 2025Large Language Model for Verilog Code Generation: Literature Review and the Road Aheadcited by 7
- 2026EvolVE: Evolutionary Search for LLM-based Verilog Generation and Optimizationcited by 7
- 2026ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Designcited by 7
- 2025ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflectioncited by 5
- 2025QiMeng-SALV: Signal-Aware Learning for Verilog Code Generationcited by 4
- 2025REvolution: An Evolutionary Framework for RTL Generation driven by Large Language Modelscited by 4
- 2025Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMscited by 2
- 2025EvoVerilog: Large Langugage Model Assisted Evolution of Verilog Codecited by 2
- 2026Configuration Over Selection: Hyperparameter Sensitivity Exceeds Model Differences in Open-Source LLMs for RTL Generationcited by 1
12 most cited of 17 All 17 (JSON)
- 2026RTLCurator: Label-Efficient Data Curation for RTL Generation31 Jul 2026
- 2026HierSVA: A Data Synthesis Pipeline, Dataset, and Benchmark for LLM-Driven Hierarchical Hardware Formal Verification9 Jun 2026
- 2026Alpha-RTL: Test-Time Training for RTL Hardware Optimization3 Jun 2026
- 2026LEGO: An LLM Skill-Based Front-End Design Generation Platform25 Apr 2026
- 2026AutoPPA: Automated Circuit PPA Optimization via Contrastive Code-based Rule Library Learning20 Apr 2026
- 2026Configuration Over Selection: Hyperparameter Sensitivity Exceeds Model Differences in Open-Source LLMs for RTL Generation18 Apr 2026
- 2026ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Design29 Jan 2026
- 2026EvolVE: Evolutionary Search for LLM-based Verilog Generation and Optimization26 Jan 2026
- 2025Large Language Model for Verilog Code Generation: Literature Review and the Road Ahead29 Oct 2025
- 2025REvolution: An Evolutionary Framework for RTL Generation driven by Large Language Models24 Oct 2025
- 2025QiMeng-SALV: Signal-Aware Learning for Verilog Code Generation22 Oct 2025
- 2025RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs22 Jul 2025
12 newest of 17 All 17 (JSON)