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EDA-Aware RTL Generation with Large Language Models

arXiv 2412.04485 ↗First posted 21 Nov 2024cs.AR cs.AIcited by 0

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Abstract (arXiv)

Large Language Models (LLMs) have become increasingly popular for generating RTL code. However, producing error-free RTL code in a zero-shot setting remains highly challenging for even state-of-the-art LLMs, often leading to issues that require manual, iterative refinement. This additional debugging process can dramatically increase the verification workload, underscoring the need for robust, automated correction mechanisms to ensure code correctness from the start. In this work, we introduce AIvril2, a self-verifying, LLM-agnostic agentic framework aimed at enhancing RTL code generation through iterative corrections of both syntax and functional errors. Our approach leverages a collaborative multi-agent system that incorporates feedback from error logs generated by EDA tools to automatically identify and resolve design flaws. Experimental results, conducted on the VerilogEval-Human benchmark suite, demonstrate that our framework significantly improves code quality, achieving nearly a 3.4× enhancement over prior methods. In the best-case scenario, functional pass rates of 77% for Verilog and 66% for VHDL were obtained, thus substantially improving the reliability of LLM-driven RTL code generation.

Key facts. No citing papers in the map yet (data through 7 Oct 2026). Builds on 10 of its 18 references that are in the map. First posted on arXiv 21 Nov 2024.

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10 of 18 references.

References · 10

  1. 2024The Llama 3 Herd of Modelscited by 14,192
  2. 2022ReAct: Synergizing Reasoning and Acting in Language Modelscited by 8,355
  3. 2021Evaluating Large Language Models Trained on Codecited by 8,053
  4. 2023ChipNeMo: Domain-Adapted LLMs for Chip Designcited by 168
  5. 2023RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Modelscited by 98
  6. 2024VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Toolcited by 85
  7. 2024Towards LLM-Powered Verilog RTL Assistant: Self-Verification and Self-Correctioncited by 39
  8. 2024CodeV: Empowering LLMs with HDL Generation through Multi-Level Summarizationcited by 38
  9. 2024Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation frameworkcited by 36
  10. 2024AIvril: AI-Driven RTL Generation With Verification In-The-Loopcited by 15

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  1. 2025PEFA-AI: Advancing Open-source LLMs for RTL generation using Progressive Error Feedback Agentic-AI
  2. 2024MAGE: A Multi-Agent Engine for Automated RTL Code Generation
  3. 2025Understanding and Mitigating Errors of LLM-Generated RTL Code
  4. 2026ChipCraftBrain: Validation-First RTL Generation via Multi-Agent Orchestration
  5. 2025Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification
  6. 2025TuRTLe: A Unified Evaluation of LLMs for RTL Generation
  7. 2026VeriAgent: A Tool-Integrated Multi-Agent System with Evolving Memory for PPA-Aware RTL Code Generation
  8. 2026LLM4RTL: Tool-Assisted LLM for RTL Generation