VeriCWEty: Embedding enabled Line-Level CWE Detection in Verilog
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Abstract (arXiv)
Large Language Models (LLMs) have shown significant improvement in RTL code generation. Despite the advances, the generated code is often riddled with common vulnerabilities and weaknesses (CWEs) that can slip by untrained eyes. Attackers can often exploit these weaknesses to fulfill their nefarious motives. Existing RTL bug-detection techniques rely on rule-based checks, formal properties, or coarse-grained structural analysis, which either fail to capture semantic vulnerabilities or lack precise localization. In our work, we bridge this gap by proposing an embedding-based bug-detection framework that detects and classifies bugs at both module and line-level granularity. Our method achieves about 89% precision in identifying common CWEs such as CWE-1244 and CWE-1245, and 96% accuracy in detecting line-level bugs.
Key facts. Cited by 2 papers in the map (data through 7 Oct 2026). Builds on 12 of its 27 references that are in the map. First posted on arXiv 15 Apr 2026.
Builds on
12 of 27 references.
References · 12
- 2024Large Language Model for Vulnerability Detection: Emerging Results and Future Directionscited by 44
- 2024LLM4SecHW: Leveraging Domain Specific Large Language Model for Hardware Debuggingcited by 18
- 2024LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trustcited by 18
- 2024All Artificial, Less Intelligence: GenAI through the Lens of Formal Verificationcited by 11
- 2024Self-HWDebug: Automation of LLM Self-Instructing for Hardware Security Verificationcited by 11
- 2025BugWhisperer: Fine-Tuning LLMs for SoC Hardware Vulnerability Detectioncited by 5
- 2025TrojanLoC: LLM-based Framework for RTL Trojan Localizationcited by 5
- 2025LASHED: LLMs And Static Hardware Analysis for Early Detection of RTL Bugscited by 4
- 2022Don't CWEAT It: Toward CWE Analysis Techniques in Early Stages of Hardware Designcited by 3
- 2025VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Codecited by 3
- 2024Security Properties for Open-Source Hardware Designscited by 2
- 2025VerilogLAVD: LLM-Aided Rule Generation for Vulnerability Detection in Verilogcited by 2
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Citing papers per year: 2026: 2.
2 papers.