NetDeTox: Adversarial and Efficient Evasion of Hardware-Security GNNs via RL-LLM Orchestration
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Abstract (arXiv)
Graph neural networks (GNNs) have shown promise in hardware security by learning structural motifs from netlist graphs. However, this reliance on motifs makes GNNs vulnerable to adversarial netlist rewrites; even small-scale edits can mislead GNN predictions. Existing adversarial approaches, ranging from synthesis-recipe perturbations to gate transformations, come with high design overheads. We present NetDeTox, an automated end-to-end framework that orchestrates large language models (LLMs) with reinforcement learning (RL) in a systematic manner, enabling focused local rewriting. The RL agent identifies netlist components critical for GNN-based reasoning, while the LLM devises rewriting plans to diversify motifs that preserve functionality. Iterative feedback between the RL and LLM stages refines adversarial rewritings to limit overheads. Compared to the SOTA work AttackGNN, NetDeTox successfully degrades the effectiveness of all security schemes with fewer rewrites and substantially lower area overheads (reductions of 54.50% for GNN-RE, 25.44% for GNN4IP, and 41.04% for OMLA, respectively). For GNN4IP, ours can even optimize/reduce the original benchmarks' area, in particular for larger circuits, demonstrating the practicality and scalability of NetDeTox.
Key facts. Cited by 9 papers in the map (data through 14 Oct 2026). Builds on 17 of its 33 references that are in the map. First posted on arXiv 27 Nov 2025.
Builds on
17 of 33 references.
References · 17
- 2024Understanding the planning of LLM agents: A surveycited by 421
- 2023CodePlan: Repository-level Coding using LLMs and Planningcited by 140
- 2024AutoBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Designcited by 41
- 2024Survey of different Large Language Model Architectures: Trends, Benchmarks, and Challengescited by 32
- 2024AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMscited by 31
- 2024LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trustcited by 20
- 2021GNN4IP: Graph Neural Network for Hardware Intellectual Property Piracy Detectioncited by 14
- 2025VeriContaminated: Assessing LLM-Driven Verilog Coding for Data Contaminationcited by 12
- 2025SALAD: Systematic Assessment of Machine Unlearning on LLM-Aided Hardware Designcited by 12
- 2025VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Codingcited by 11
- 2024Retrieval-Guided Reinforcement Learning for Boolean Circuit Minimizationcited by 10
- 2025NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graphcited by 9
5 more
- 2024LLMPirate: LLMs for Black-box Hardware IP Piracycited by 7
- 2025Veritas: Deterministic Verilog Code Synthesis from LLM-Generated Conjunctive Normal Formcited by 7
- 2024AttackGNN: Red-Teaming GNNs in Hardware Security Using Reinforcement Learningcited by 6
- 2024Circuit Transformer: A Transformer That Preserves Logical Equivalencecited by 5
- 2020ATPG-Guided Fault Injection Attacks on Logic Lockingcited by 2
Built on by
Citing papers per year: 2026: 9.
9 papers.
- 2026HarmChip: Evaluating Hardware Security Centric LLM Safety via Jailbreak Benchmarkingcited by 3
- 2026TrojanGYM: A Detector-in-the-Loop LLM for Adaptive RTL Hardware Trojan Insertioncited by 2
- 2026AI In Cybersecurity Education -- Scalable Agentic CTF Design Principles and Educational Outcomescited by 1
- 2026Configuration Over Selection: Hyperparameter Sensitivity Exceeds Model Differences in Open-Source LLMs for RTL Generationcited by 1
- 2026LLMs for Secure Hardware Design and Related Problems: Opportunities and Challengescited by 1
- 2026Focus Session: Hardware and Software Techniques for Accelerating Multimodal Foundation Modelscited by 0
- 2026VHDLSuite: Unified Pipeline for LLM VHDL Generation with Data Synthesis and Evaluationcited by 0
- 2026Hardware Design and Security in the Era of Chiplets and LLMscited by 0
- 2026ReDIL-GNN: Resynthesis Domain Incremental Learning for Circuit Graph Neural Networkscited by 0
- 2026ReDIL-GNN: Resynthesis Domain Incremental Learning for Circuit Graph Neural Networks16 Sep 2026
- 2026Hardware Design and Security in the Era of Chiplets and LLMs5 Aug 2026
- 2026VHDLSuite: Unified Pipeline for LLM VHDL Generation with Data Synthesis and Evaluation11 Jun 2026
- 2026LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges11 May 2026
- 2026Focus Session: Hardware and Software Techniques for Accelerating Multimodal Foundation Models23 Apr 2026
- 2026Configuration Over Selection: Hyperparameter Sensitivity Exceeds Model Differences in Open-Source LLMs for RTL Generation18 Apr 2026
- 2026HarmChip: Evaluating Hardware Security Centric LLM Safety via Jailbreak Benchmarking18 Apr 2026
- 2026AI In Cybersecurity Education -- Scalable Agentic CTF Design Principles and Educational Outcomes23 Mar 2026
- 2026TrojanGYM: A Detector-in-the-Loop LLM for Adaptive RTL Hardware Trojan Insertion23 Jan 2026
Similar, not cited
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- 2025GRAPHTEXTACK: A Realistic Black-Box Node Injection Attack on LLM-Enhanced GNNs
- 2025G-Safeguard: A Topology-Guided Security Lens and Treatment on LLM-based Multi-agent Systems
- 2025The Resurgence of GCG Adversarial Attacks on Large Language Models
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