mlsanityData to 14 Oct 2026

AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMs

arXiv 2402.00386 ↗First posted 1 Feb 2024cs.ARcited by 31

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Abstract (arXiv)

Assertion-based verification (ABV) is a critical method for ensuring design circuits comply with their architectural specifications, which are typically described in natural language. This process often requires human interpretation by verification engineers to convert these specifications into functional verification assertions. Existing methods for generating assertions from natural language specifications are limited to sentences extracted by engineers, discouraging its practical application. In this work, we present AssertLLM, an automatic assertion generation framework that processes complete specification files. AssertLLM breaks down the complex task into three phases, incorporating three customized Large Language Models (LLMs) for extracting structural specifications, mapping signal definitions, and generating assertions. Our evaluation of AssertLLM on a full design, encompassing 23 I/O signals, demonstrates that 89% of the generated assertions are both syntactically and functionally accurate.

Key facts. Cited by 31 papers in the map (data through 14 Oct 2026). First posted on arXiv 1 Feb 2024.

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Citing papers per year: 2024: 5; 2025: 17; 2026: 9.

31 papers.

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  1. 2024HDLdebugger: Streamlining HDL debugging with Large Language Modelscited by 26
  2. 2024RTL-Breaker: Assessing the Security of LLMs against Backdoor Attacks on HDL Code Generationcited by 15
  3. 2025RealBench: Benchmarking Verilog Generation Models with Real-World IP Designscited by 14
  4. 2025AssertionForge: Enhancing Formal Verification Assertion Generation with Structured Representation of Specifications and RTLcited by 13
  5. 2025VeriContaminated: Assessing LLM-Driven Verilog Coding for Data Contaminationcited by 12
  6. 2025SALAD: Systematic Assessment of Machine Unlearning on LLM-Aided Hardware Designcited by 12
  7. 2024Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generationcited by 11
  8. 2025VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Codingcited by 11
  9. 2024SPICEPilot: Navigating SPICE Code Generation and Simulation with AI Guidancecited by 10
  10. 2024FVEval: Understanding Language Model Capabilities in Formal Verification of Digital Hardwarecited by 10
  11. 2025Enhancing Large Language Models for Hardware Verification: A Novel SystemVerilog Assertion Datasetcited by 10
  12. 2025NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graphcited by 9
19 more
  1. 2025From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verificationcited by 9
  2. 2025Circuit Representation Learning with Masked Gate Modeling and Verilog-AIG Alignmentcited by 8
  3. 2025Are LLMs Ready for Practical Adoption for Assertion Generation?cited by 6
  4. 2025Hey AI, Generate Me a Hardware Code! Agentic AI-based Hardware Design & Verificationcited by 5
  5. 2025CorrectHDL: Agentic HDL Design with LLMs Leveraging High-Level Synthesis as Referencecited by 3
  6. 2026Can Agents Secure Hardware? Evaluating Agentic LLM-Driven Obfuscation for IP Protectioncited by 3
  7. 2026AssertLLM2: A Comprehensive LLM Benchmark for Assertion Generation from Design Specificationscited by 3
  8. 2025TPU-Gen: LLM-Driven Custom Tensor Processing Unit Generatorcited by 2
  9. 2025SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refinecited by 2
  10. 2025GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignmentcited by 1
  11. 2025ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocolscited by 1
  12. 2026FVRuleLearner: Operator-Level Reasoning Tree (Op-Tree)-Based Rules Learning for Formal Verificationcited by 1
  13. 2026Is Agentic AI Ready for Real-World Hardware Engineering? A Deep Dive with Phoenix-benchcited by 1
  14. 2025Advancing AI-assisted Hardware Design with Hierarchical Decentralized Training and Personalized Inference-Time Optimizationcited by 0
  15. 2026Autoformalizing Memory Specifications with Agentscited by 0
  16. 2026HierSVA: A Data Synthesis Pipeline, Dataset, and Benchmark for LLM-Driven Hierarchical Hardware Formal Verificationcited by 0
  17. 2026PICasso: An AI-Enabled Design Framework for Autonomous Optimization of Silicon Photonic Devicescited by 0
  18. 2026AgentDV: Closed-Loop Agentic AI for Hardware Design Verificationcited by 0
  19. 2026SpecRead: A Benchmark for Measuring Whether Language Models Understand Hardware Specificationscited by 0