mlsanityData to 14 Oct 2026

LLM-Aided Testbench Generation and Bug Detection for Finite-State Machines

arXiv 2406.17132 ↗First posted 24 Jun 2024cs.ARcited by 17

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Abstract (arXiv)

This work investigates the potential of tailoring Large Language Models (LLMs), specifically GPT3.5 and GPT4, for the domain of chip testing. A key aspect of chip design is functional testing, which relies on testbenches to evaluate the functionality and coverage of Register-Transfer Level (RTL) designs. We aim to enhance testbench generation by incorporating feedback from commercial-grade Electronic Design Automation (EDA) tools into LLMs. Through iterative feedback from these tools, we refine the testbenches to achieve improved test coverage. Our case studies present promising results, demonstrating that this approach can effectively enhance test coverage. By integrating EDA tool feedback, the generated testbenches become more accurate in identifying potential issues in the RTL design. Furthermore, we extended our study to use this enhanced test coverage framework for detecting bugs in the RTL implementations

Key facts. Cited by 17 papers in the map (data through 14 Oct 2026). First posted on arXiv 24 Jun 2024.

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Cited by year (2026 to 14 Oct)

Citing papers per year: 2024: 3; 2025: 6; 2026: 8.

17 papers.

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  1. 2024CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repaircited by 42
  2. 2024RTL-Breaker: Assessing the Security of LLMs against Backdoor Attacks on HDL Code Generationcited by 15
  3. 2025VeriContaminated: Assessing LLM-Driven Verilog Coding for Data Contaminationcited by 12
  4. 2025SALAD: Systematic Assessment of Machine Unlearning on LLM-Aided Hardware Designcited by 12
  5. 2025VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Codingcited by 11
  6. 2024Are LLMs Any Good for High-Level Synthesis?cited by 6
  7. 2025ChipMind: Retrieval-Augmented Reasoning for Long-Context Circuit Design Specificationscited by 4
  8. 2026UCAgent: An End-to-End Agent for Block-Level Functional Verificationcited by 2
  9. 2025AutoFSM: A Multi-agent Framework for FSM Code Generation with IR and SystemC-Based Testingcited by 1
  10. 2026GUIDE: GenAI Units In Digital Design Educationcited by 1
  11. 2026LLMs for Secure Hardware Design and Related Problems: Opportunities and Challengescited by 1
  12. 2025Legal Document Summarization: Enhancing Judicial Efficiency through Automation Detectioncited by 0
5 more
  1. 2026Designing FSMs Specifications from Requirements with GPT 4.0cited by 0
  2. 2026EstRTL: Functional Estimation Guided RTL Code Generationcited by 0
  3. 2026Hardware Design and Security in the Era of Chiplets and LLMscited by 0
  4. 2026BEHAVE: Functional Behavior Modeling Enables Self-Improving Agents for Hardware Design and Verificationcited by 0
  5. 2026A Survey on LLM-Integrated Hardware Design Verificationcited by 0