mlsanityData to 7 Oct 2026

HaVen: Hallucination-Mitigated LLM for Verilog Code Generation Aligned with HDL Engineers

arXiv 2501.04908 ↗First posted 9 Jan 2025cs.PL cs.ARcited by 24

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Abstract (arXiv)

Recently, the use of large language models (LLMs) for Verilog code generation has attracted great research interest to enable hardware design automation. However, previous works have shown a gap between the ability of LLMs and the practical demands of hardware description language (HDL) engineering. This gap includes differences in how engineers phrase questions and hallucinations in the code generated. To address these challenges, we introduce HaVen, a novel LLM framework designed to mitigate hallucinations and align Verilog code generation with the practices of HDL engineers. HaVen tackles hallucination issues by proposing a comprehensive taxonomy and employing a chain-of-thought (CoT) mechanism to translate symbolic modalities (e.g. truth tables, state diagrams, etc.) into accurate natural language descriptions. Furthermore, HaVen bridges this gap by using a data augmentation strategy. It synthesizes high-quality instruction-code pairs that match real HDL engineering practices. Our experiments demonstrate that HaVen significantly improves the correctness of Verilog code generation, outperforming state-of-the-art LLM-based Verilog generation methods on VerilogEval and RTLLM benchmark. HaVen is publicly available at https://github.com/Intelligent-Computing-Research-Group/HaVen.

Key facts. Cited by 24 papers in the map (data through 7 Oct 2026). First posted on arXiv 9 Jan 2025.

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Cited by year (2026 to 7 Oct)

Citing papers per year: 2025: 17; 2026: 7.

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  1. 2025VFlow: Discovering Optimal Agentic Workflows for Verilog Generationcited by 19
  2. 2025HDLCoRe: A Training-Free Framework for Mitigating Hallucinations in LLM-Generated HDLcited by 17
  3. 2025VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generationcited by 16
  4. 2025VeriMoA: A Mixture-of-Agents Framework for Spec-to-HDL Generationcited by 15
  5. 2025Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedbackcited by 14
  6. 2025SALAD: Systematic Assessment of Machine Unlearning on LLM-Aided Hardware Designcited by 10
  7. 2025TuRTLe: A Unified Evaluation of LLMs for RTL Generationcited by 8
  8. 2025Large Language Model for Verilog Code Generation: Literature Review and the Road Aheadcited by 7
  9. 2025ResBench: Benchmarking LLM-Generated FPGA Designs with Resource Awarenesscited by 5
  10. 2025VeriDispatcher: Multi-Model Dispatching through Pre-Inference Difficulty Prediction for RTL Generation Optimizationcited by 5
  11. 2025NotSoTiny: A Large, Living Benchmark for RTL Code Generationcited by 3
  12. 2026COEVO: Co-Evolutionary Framework for Joint Functional Correctness and PPA Optimization in LLM-Based RTL Generationcited by 3
12 more
  1. 2025hdl2v: A Code Translation Dataset for Enhanced LLM Verilog Generationcited by 2
  2. 2025VeriGRAG: Enhancing LLM-Based Verilog Code Generation with Structure-Aware Soft Promptscited by 2
  3. 2025EARL: Entropy-Aware RL Alignment of LLMs for Reliable RTL Code Generationcited by 2
  4. 2025QiMeng-CRUX: Narrowing the Gap Between Natural Language and Verilog via Core Refined Understanding eXpression for Circuit Designcited by 1
  5. 2026TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilogcited by 1
  6. 2025RocketPPA: Code-Level Power, Performance, and Area Prediction via LLM and Mixture of Expertscited by 0
  7. 2025When Forgetting Builds Reliability: LLM Unlearning for Reliable Hardware Code Generationcited by 0
  8. 2026AutoPPA: Automated Circuit PPA Optimization via Contrastive Code-based Rule Library Learningcited by 0
  9. 2026CASS-RTL: Correctness-Aware Subspace Steering for RTL Generation with LLMscited by 0
  10. 2026LLM4RTL: Tool-Assisted LLM for RTL Generationcited by 0
  11. 2026Agentic Electronic Design Automation: A Handoff Perspectivecited by 0
  12. 2026Benchmarking LLMs for Verilog Design Flowscited by 0