DeepGate3: Towards Scalable Circuit Representation Learning
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Abstract (arXiv)
Circuit representation learning has shown promising results in advancing the field of Electronic Design Automation (EDA). Existing models, such as DeepGate Family, primarily utilize Graph Neural Networks (GNNs) to encode circuit netlists into gate-level embeddings. However, the scalability of GNN-based models is fundamentally constrained by architectural limitations, impacting their ability to generalize across diverse and complex circuit designs. To address these challenges, we introduce DeepGate3, an enhanced architecture that integrates Transformer modules following the initial GNN processing. This novel architecture not only retains the robust gate-level representation capabilities of its predecessor, DeepGate2, but also enhances them with the ability to model subcircuits through a novel pooling transformer mechanism. DeepGate3 is further refined with multiple innovative supervision tasks, significantly enhancing its learning process and enabling superior representation of both gate-level and subcircuit structures. Our experiments demonstrate marked improvements in scalability and generalizability over traditional GNN-based approaches, establishing a significant step forward in circuit representation learning technology.
Key facts. Cited by 26 papers in the map (data through 14 Oct 2026). Builds on 28 of its 53 references that are in the map. First posted on arXiv 15 Jul 2024.
Builds on
28 of 53 references.
References · 28
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Citing papers per year: 2025: 19; 2026: 7.
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- 2025DeepCircuitX: A Comprehensive Repository-Level Dataset for RTL Code Understanding, Generation, and PPA Analysiscited by 21
- 2025DeepGate4: Efficient and Effective Representation Learning for Circuit Design at Scalecited by 12
- 2025NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graphcited by 9
- 2025Revolution or Hype? Seeking the Limits of Large Models in Hardware Designcited by 9
- 2025Circuit Representation Learning with Masked Gate Modeling and Verilog-AIG Alignmentcited by 8
- 2025MMCircuitEval: A Comprehensive Multimodal Circuit-Focused Benchmark for Evaluating LLMscited by 6
- 2025DeepCell: Self-Supervised Multiview Fusion for Circuit Representation Learningcited by 3
- 2025DICE: Device-level Integrated Circuits Encoder with Graph Contrastive Pretrainingcited by 2
- 2025Circuit-Aware SAT Solving: Guiding CDCL via Conditional Probabilitiescited by 2
- 2025GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignmentcited by 1
- 2025Functional Matching of Logic Subgraphs: Beyond Structural Isomorphismcited by 1
- 2025FuncGNN: Learning Functional Semantics of Logic Circuits with Graph Neural Networkscited by 1
14 more
- 2025Alignment Unlocks Complementarity: A Framework for Multiview Circuit Representation Learningcited by 1
- 2026R2G: A Multi-View Circuit Graph Benchmark Suite from RTL to GDSIIcited by 1
- 2025Modeling Relational Logic Circuits for And-Inverter Graph Convolutional Networkcited by 0
- 2025TRACE: Learning to Compute on Circuit Graphscited by 0
- 2025Learning Representations Through Contrastive Neural Model Checkingcited by 0
- 2025BoolSkeleton: Boolean Network Skeletonization via Homogeneous Pattern Reductioncited by 0
- 2025InF-ATPG: Intelligent FFR-Driven ATPG with Advanced Circuit Representation Guided Reinforcement Learningcited by 0
- 2025ReVEAL: GNN-Guided Reverse Engineering for Formal Verification of Optimized Multiplierscited by 0
- 2026GNN-based Path-aware multi-view Circuit Learning for Technology Mappingcited by 0
- 2026Wrong Code, Right Structure: Learning Netlist Representations from Imperfect LLM-Generated RTLcited by 0
- 2026KCLNet: Electrically Equivalence-Oriented Graph Representation Learning for Analog Circuitscited by 0
- 2026Graph Computation Meets Circuit Algebra: A Task-Aligned Analysis of Graph Neural Networks for Electronic Design Automationcited by 0
- 2026Beyond Flat Netlist: Hierarchical Graph Representation Learning for Scalable Analysis of Sequential Circuitscited by 0
- 2026ReDIL-GNN: Resynthesis Domain Incremental Learning for Circuit Graph Neural Networkscited by 0
- 2026ReDIL-GNN: Resynthesis Domain Incremental Learning for Circuit Graph Neural Networks16 Sep 2026
- 2026Beyond Flat Netlist: Hierarchical Graph Representation Learning for Scalable Analysis of Sequential Circuits28 Aug 2026
- 2026Graph Computation Meets Circuit Algebra: A Task-Aligned Analysis of Graph Neural Networks for Electronic Design Automation8 May 2026
- 2026R2G: A Multi-View Circuit Graph Benchmark Suite from RTL to GDSII9 Apr 2026
- 2026KCLNet: Electrically Equivalence-Oriented Graph Representation Learning for Analog Circuits25 Mar 2026
- 2026Wrong Code, Right Structure: Learning Netlist Representations from Imperfect LLM-Generated RTL10 Mar 2026
- 2026GNN-based Path-aware multi-view Circuit Learning for Technology Mapping14 Jan 2026
- 2025ReVEAL: GNN-Guided Reverse Engineering for Formal Verification of Optimized Multipliers24 Dec 2025
- 2025InF-ATPG: Intelligent FFR-Driven ATPG with Advanced Circuit Representation Guided Reinforcement Learning25 Nov 2025
- 2025BoolSkeleton: Boolean Network Skeletonization via Homogeneous Pattern Reduction4 Nov 2025
- 2025Learning Representations Through Contrastive Neural Model Checking2 Oct 2025
- 2025TRACE: Learning to Compute on Circuit Graphs26 Sep 2025
14 more
- 2025Alignment Unlocks Complementarity: A Framework for Multiview Circuit Representation Learning25 Sep 2025
- 2025Revolution or Hype? Seeking the Limits of Large Models in Hardware Design5 Sep 2025
- 2025Modeling Relational Logic Circuits for And-Inverter Graph Convolutional Network16 Aug 2025
- 2025Circuit-Aware SAT Solving: Guiding CDCL via Conditional Probabilities6 Aug 2025
- 2025MMCircuitEval: A Comprehensive Multimodal Circuit-Focused Benchmark for Evaluating LLMs20 Jul 2025
- 2025FuncGNN: Learning Functional Semantics of Logic Circuits with Graph Neural Networks7 Jun 2025
- 2025Functional Matching of Logic Subgraphs: Beyond Structural Isomorphism28 May 2025
- 2025GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignment13 Apr 2025
- 2025NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph12 Apr 2025
- 2025DeepCircuitX: A Comprehensive Repository-Level Dataset for RTL Code Understanding, Generation, and PPA Analysis25 Feb 2025
- 2025Circuit Representation Learning with Masked Gate Modeling and Verilog-AIG Alignment18 Feb 2025
- 2025DICE: Device-level Integrated Circuits Encoder with Graph Contrastive Pretraining13 Feb 2025
- 2025DeepCell: Self-Supervised Multiview Fusion for Circuit Representation Learning5 Feb 2025
- 2025DeepGate4: Efficient and Effective Representation Learning for Circuit Design at Scale2 Feb 2025
- 2025DeepCircuitX: A Comprehensive Repository-Level Dataset for RTL Code Understanding, Generation, and PPA Analysiscited by 21
- 2025DeepGate4: Efficient and Effective Representation Learning for Circuit Design at Scalecited by 12
- 2025NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graphcited by 9
- 2025Revolution or Hype? Seeking the Limits of Large Models in Hardware Designcited by 9
- 2025Circuit Representation Learning with Masked Gate Modeling and Verilog-AIG Alignmentcited by 8
- 2025DeepCell: Self-Supervised Multiview Fusion for Circuit Representation Learningcited by 3
- 2025DICE: Device-level Integrated Circuits Encoder with Graph Contrastive Pretrainingcited by 2
- 2025Circuit-Aware SAT Solving: Guiding CDCL via Conditional Probabilitiescited by 2
- 2025Functional Matching of Logic Subgraphs: Beyond Structural Isomorphismcited by 1
- 2025FuncGNN: Learning Functional Semantics of Logic Circuits with Graph Neural Networkscited by 1
- 2025Alignment Unlocks Complementarity: A Framework for Multiview Circuit Representation Learningcited by 1
- 2026R2G: A Multi-View Circuit Graph Benchmark Suite from RTL to GDSIIcited by 1
12 most cited of 24 All 24 (JSON)
- 2026ReDIL-GNN: Resynthesis Domain Incremental Learning for Circuit Graph Neural Networks16 Sep 2026
- 2026Beyond Flat Netlist: Hierarchical Graph Representation Learning for Scalable Analysis of Sequential Circuits28 Aug 2026
- 2026Graph Computation Meets Circuit Algebra: A Task-Aligned Analysis of Graph Neural Networks for Electronic Design Automation8 May 2026
- 2026R2G: A Multi-View Circuit Graph Benchmark Suite from RTL to GDSII9 Apr 2026
- 2026KCLNet: Electrically Equivalence-Oriented Graph Representation Learning for Analog Circuits25 Mar 2026
- 2026Wrong Code, Right Structure: Learning Netlist Representations from Imperfect LLM-Generated RTL10 Mar 2026
- 2026GNN-based Path-aware multi-view Circuit Learning for Technology Mapping14 Jan 2026
- 2025ReVEAL: GNN-Guided Reverse Engineering for Formal Verification of Optimized Multipliers24 Dec 2025
- 2025InF-ATPG: Intelligent FFR-Driven ATPG with Advanced Circuit Representation Guided Reinforcement Learning25 Nov 2025
- 2025BoolSkeleton: Boolean Network Skeletonization via Homogeneous Pattern Reduction4 Nov 2025
- 2025Learning Representations Through Contrastive Neural Model Checking2 Oct 2025
- 2025TRACE: Learning to Compute on Circuit Graphs26 Sep 2025
12 newest of 24 All 24 (JSON)