Exploring LLM-based Verilog Code Generation with Data-Efficient Fine-Tuning and Testbench Automation
Not on the map. Why?
Abstract (arXiv)
Recent advances in large language models have improved code generation, but their use in hardware description languages is still limited. Moreover, training data and testbenches for these models are often scarce. This paper presents a workflow that uses multi-agent models to generate testbenches for high-quality fine-tuning data. By automating testbench creation, the fine-tuned model for the specification-to-Verilog task achieves performance comparable to state-of-the-art methods on the refined VerilogEval v2 benchmark while using less training data. This study provides a basis for future work on LLM-based HDL generation and automated verification.
Key facts. No citing papers in the map yet (data through 14 Oct 2026). Builds on 11 of its 15 references that are in the map. First posted on arXiv 16 Apr 2026.
Builds on
11 of 15 references.
References · 11
- 2020Language Models are Few-Shot Learnerscited by 32,419
- 2023GPT-4 Technical Reportcited by 18,396
- 2025DeepSeek-R1: Incentivizing Reasoning Capability in LLMs via Reinforcement Learningcited by 6,330
- 2025DAPO: An Open-Source LLM Reinforcement Learning System at Scalecited by 2,810
- 2024Qwen2.5-Coder Technical Reportcited by 1,203
- 2024Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generationcited by 45
- 2025QiMeng-CodeV-R1: Reasoning-Enhanced Verilog Generationcited by 35
- 2025DeepCircuitX: A Comprehensive Repository-Level Dataset for RTL Code Understanding, Generation, and PPA Analysiscited by 21
- 2024PyraNet: A Multi-Layered Hierarchical Dataset for Verilogcited by 19
- 2025VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generationcited by 16
- 2025Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedbackcited by 14
Built on by
Not cited yet.