CircuitNet: An Open-Source Dataset for Machine Learning Applications in Electronic Design Automation (EDA)
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Abstract (arXiv)
The electronic design automation (EDA) community has been actively exploring machine learning (ML) for very large-scale integrated computer-aided design (VLSI CAD). Many studies explored learning-based techniques for cross-stage prediction tasks in the design flow to achieve faster design convergence. Although building ML models usually requires a large amount of data, most studies can only generate small internal datasets for validation because of the lack of large public datasets. In this essay, we present the first open-source dataset called CircuitNet for ML tasks in VLSI CAD.
Key facts. Cited by 10 papers in the map (data through 7 Oct 2026). Builds on 2 of its 5 references that are in the map. First posted on arXiv 1 Aug 2022.
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2 of 5 references.
References · 2
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Citing papers per year: 2023: 4; 2024: 1; 2025: 1; 2026: 4.
10 papers.
- 2023CktGNN: Circuit Graph Neural Network for Electronic Design Automationcited by 55
- 2025DeepCircuitX: A Comprehensive Repository-Level Dataset for RTL Code Understanding, Generation, and PPA Analysiscited by 21
- 2023HLSDataset: Open-Source Dataset for ML-Assisted FPGA Design using High Level Synthesiscited by 4
- 2024PDNNet: PDN-Aware GNN-CNN Heterogeneous Network for Dynamic IR Drop Predictioncited by 3
- 2023HybridNet: Dual-Branch Fusion of Geometrical and Topological Views for VLSI Congestion Predictioncited by 2
- 2023EDALearn: A Comprehensive RTL-to-Signoff EDA Benchmark for Democratized and Reproducible ML for EDA Researchcited by 2
- 2026R2G: A Multi-View Circuit Graph Benchmark Suite from RTL to GDSIIcited by 0
- 2026Graph Computation Meets Circuit Algebra: A Task-Aligned Analysis of Graph Neural Networks for Electronic Design Automationcited by 0
- 2026ParasGB: A Graph Benchmark Suite for Parasitic Estimation on AMS Circuitscited by 0
- 2026CARVE: Breaking Data Barriers in Chip Placement by Harnessing Reusable Expertisecited by 0
- 2026CARVE: Breaking Data Barriers in Chip Placement by Harnessing Reusable Expertise27 Sep 2026
- 2026ParasGB: A Graph Benchmark Suite for Parasitic Estimation on AMS Circuits25 Jul 2026
- 2026Graph Computation Meets Circuit Algebra: A Task-Aligned Analysis of Graph Neural Networks for Electronic Design Automation8 May 2026
- 2026R2G: A Multi-View Circuit Graph Benchmark Suite from RTL to GDSII9 Apr 2026
- 2025DeepCircuitX: A Comprehensive Repository-Level Dataset for RTL Code Understanding, Generation, and PPA Analysis25 Feb 2025
- 2024PDNNet: PDN-Aware GNN-CNN Heterogeneous Network for Dynamic IR Drop Prediction27 Mar 2024
- 2023EDALearn: A Comprehensive RTL-to-Signoff EDA Benchmark for Democratized and Reproducible ML for EDA Research4 Dec 2023
- 2023CktGNN: Circuit Graph Neural Network for Electronic Design Automation31 Aug 2023
- 2023HybridNet: Dual-Branch Fusion of Geometrical and Topological Views for VLSI Congestion Prediction7 May 2023
- 2023HLSDataset: Open-Source Dataset for ML-Assisted FPGA Design using High Level Synthesis17 Feb 2023