ChipMEM: Verification-Grounded Memory for EDA Agents

arXiv 2609.27067 ↗First posted 22 Sep 2026cs.LG cs.CLcited by 0

On the map: LLM agents and tool use → Agent skill learning and evolution

Abstract (arXiv)

Large language model (LLM)-based agents use Electronic Design Automation (EDA) tools to generate and revise register-transfer-level (RTL) designs under synthesis and verification feedback. Recent methods learn from this feedback by distilling reusable skills from execution traces or by training on rewards derived from EDA-tools. Both methods are typically evaluated on the tasks that produced the experience. Repeated access to benchmark feedback on the same task can reward task-specific revision rather than creating reusable knowledge that transfers. We introduce ChipMEM, a verification-grounded memory layer for EDA agents. It combines cross-task procedural memory with within-trajectory statistical guidance. Its procedural component distills and stores a skill only after it passes synthesis, simulation, or formal checks, rather than relying on model self-assessments. A Bayesian component maintains hierarchical Beta estimates over tool-call outcomes and ranks recovery strategies that succeeded under comparable errors. A common adapter applies the same memory interface to RTL optimization and testbench-generation agents while preserving each domain's tools and acceptance criteria. We measure performance on training tasks and evaluate whether learned skills transfer to unseen tasks. On RTLRewriter-Bench, under matched model and tool settings, ChipMEM produces equivalence-passing outputs on 39/54 scored designs versus 35/54 without memory; on the 49-design short suite, mean area improvement is 8.69% versus 5.66%. On held-out CVDP tasks, ChipMEM with a frozen procedural library achieves 20/20 accepted outcomes versus 18/20 without memory in a single evaluation per setting.

Key facts. No citing papers in the map yet (data through 14 Oct 2026). Placed in Agent skill learning and evolution, one of 16 directions in LLM agents and tool use. Builds on 20 of its 27 references that are in the map. First posted on arXiv 22 Sep 2026.

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2026EvolVE: Evolutionary Search for LLM-based Verilog Generation and Optimizationcited by 7
2026Dr. RTL: Autonomous Agentic RTL Optimization through Tool-Grounded Self-Improvementcited by 6
2026Agentic Hardware Design as Repository-Level Code Evolutioncited by 6

6 more

2025ChipSeek: Optimizing Verilog Generation via EDA-Integrated Reinforcement Learningcited by 5
2026A New Benchmark for the Appropriate Evaluation of RTL Code Optimizationcited by 5
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2025EARL: Entropy-Aware RL Alignment of LLMs for Reliable RTL Code Generationcited by 2
2026Alpha-RTL: Test-Time Training for RTL Hardware Optimizationcited by 2
2026RTLScout: Joint Agentic Code and Synthesis Optimization for Efficient Digital Circuitscited by 2

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