ZeroSim: Zero-Shot Analog Circuit Evaluation with Unified Transformer Embeddings
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Abstract (arXiv)
Although recent advancements in learning-based analog circuit design automation have tackled tasks such as topology generation, device sizing, and layout synthesis, efficient performance evaluation remains a major bottleneck. Traditional SPICE simulations are time-consuming, while existing machine learning methods often require topology-specific retraining or manual substructure segmentation for fine-tuning, hindering scalability and adaptability. In this work, we propose ZeroSim, a transformer-based performance modeling framework designed to achieve robust in-distribution generalization across trained topologies under novel parameter configurations and zero-shot generalization to unseen topologies without any fine-tuning. We apply three key enabling strategies: (1) a diverse training corpus of 3.6 million instances covering over 60 amplifier topologies, (2) unified topology embeddings leveraging global-aware tokens and hierarchical attention to robustly generalize to novel circuits, and (3) a topology-conditioned parameter mapping approach that maintains consistent structural representations independent of parameter variations. Our experimental results demonstrate that ZeroSim significantly outperforms baseline models such as multilayer perceptrons, graph neural networks and transformers, delivering accurate zero-shot predictions across different amplifier topologies. Additionally, when integrated into a reinforcement learning-based parameter optimization pipeline, ZeroSim achieves a remarkable speedup (13x) compared to conventional SPICE simulations, underscoring its practical value for a wide range of analog circuit design automation tasks.
Key facts. Cited by 2 papers in the map (data through 14 Oct 2026). Builds on 20 of its 37 references that are in the map. First posted on arXiv 10 Nov 2025.
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20 of 37 references.
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8 more
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Citing papers per year: 2025: 1; 2026: 1.
2 papers.
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- 2026OSIRIS: Bridging Analog Circuit Design and Machine Learning with Scalable Dataset Generation
- 2026ARCS: Autoregressive Circuit Synthesis with Topology-Aware Graph Attention and Spec Conditioning
- 2026EXPLORE: Exploration with Guided Search for Analog Topology Generation using Language Models
- 2025TopoSizing: An LLM-aided Framework of Topology-based Understanding and Sizing for AMS Circuits
- 2024AnalogXpert: Automating Analog Topology Synthesis by Incorporating Circuit Design Expertise into Large Language Models
- 2025Graph Neural Networks Based Analog Circuit Link Prediction
- 2025AnalogCoder-Pro: Unifying Analog Circuit Generation and Optimization via Multi-modal LLMs
- 2026AaLLM: An End-to-End Analog Circuit Design Framework from Topology Generation to Sizing Using Large Language Models