RoSE-Opt: Robust and Efficient Analog Circuit Parameter Optimization with Knowledge-infused Reinforcement Learning
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Abstract (arXiv)
This paper proposes a learning framework, RoSE-Opt, to achieve robust and efficient analog circuit parameter optimization. RoSE-Opt has two important features. First, it incorporates key domain knowledge of analog circuit design, such as circuit topology, couplings between circuit specifications, and variations of process, supply voltage, and temperature, into the learning loop. This strategy facilitates the training of an artificial agent capable of achieving design goals by identifying device parameters that are optimal and robust. Second, it exploits a two-level optimization method, that is, integrating Bayesian optimization (BO) with reinforcement learning (RL) to improve sample efficiency. In particular, BO is used for a coarse yet quick search of an initial starting point for optimization. This sets a solid foundation to efficiently train the RL agent with fewer samples. Experimental evaluations on benchmarking circuits show promising sample efficiency, extraordinary figure-of-merit in terms of design efficiency and design success rate, and Pareto optimality in circuit performance of our framework, compared to previous methods. Furthermore, this work thoroughly studies the performance of different RL optimization algorithms, such as Deep Deterministic Policy Gradients (DDPG) with an off-policy learning mechanism and Proximal Policy Optimization (PPO) with an on-policy learning mechanism. This investigation provides users with guidance on choosing the appropriate RL algorithms to optimize the device parameters of analog circuits. Finally, our study also demonstrates RoSE-Opt's promise in parasitic-aware device optimization for analog circuits. In summary, our work reports a knowledge-infused BO-RL design automation framework for reliable and efficient optimization of analog circuits' device parameters.
Key facts. Cited by 9 papers in the map (data through 7 Oct 2026). First posted on arXiv 27 Jul 2024.
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Citing papers per year: 2025: 6; 2026: 3.
9 papers.
- 2025AnalogGenie: A Generative Engine for Automatic Discovery of Analog Circuit Topologiescited by 35
- 2025HeaRT: A Hierarchical Circuit Reasoning Tree-Based Agentic Framework for AMS Design Optimizationcited by 5
- 2025DICE: Device-level Integrated Circuits Encoder with Graph Contrastive Pretrainingcited by 2
- 2025ZeroSim: Zero-Shot Analog Circuit Evaluation with Unified Transformer Embeddingscited by 2
- 2025Emerging ML-AI Techniques for Analog and RF EDAcited by 1
- 2026PowerGenie: Analytically-Guided Evolutionary Discovery of Superior Reconfigurable Power Converterscited by 1
- 2026ORACLE: A Multi-Objective Reinforcement Learning-Based Analog Circuit Design Optimizer with Large Language Models-Guided Explorationcited by 1
- 2025D2S-FLOW: Automated Parameter Extraction from Datasheets for SPICE Model Generation Using Large Language Modelscited by 0
- 2026AgenticSizing: A Large Language Model-based Multi-Agent Framework for Analog Circuit Sizingcited by 0
- 2026AgenticSizing: A Large Language Model-based Multi-Agent Framework for Analog Circuit Sizing22 Sep 2026
- 2026ORACLE: A Multi-Objective Reinforcement Learning-Based Analog Circuit Design Optimizer with Large Language Models-Guided Exploration5 Aug 2026
- 2026PowerGenie: Analytically-Guided Evolutionary Discovery of Superior Reconfigurable Power Converters29 Jan 2026
- 2025HeaRT: A Hierarchical Circuit Reasoning Tree-Based Agentic Framework for AMS Design Optimization24 Nov 2025
- 2025ZeroSim: Zero-Shot Analog Circuit Evaluation with Unified Transformer Embeddings10 Nov 2025
- 2025Emerging ML-AI Techniques for Analog and RF EDA12 May 2025
- 2025AnalogGenie: A Generative Engine for Automatic Discovery of Analog Circuit Topologies28 Feb 2025
- 2025D2S-FLOW: Automated Parameter Extraction from Datasheets for SPICE Model Generation Using Large Language Models23 Feb 2025
- 2025DICE: Device-level Integrated Circuits Encoder with Graph Contrastive Pretraining13 Feb 2025