R2G: A Multi-View Circuit Graph Benchmark Suite from RTL to GDSII
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Abstract (arXiv)
Graph neural networks (GNNs) are increasingly applied to physical design tasks such as congestion prediction and wirelength estimation, yet progress is hindered by inconsistent circuit representations and the absence of controlled evaluation protocols. We present R2G (RTL-to-GDSII), a multi-view circuit-graph benchmark suite that standardizes five stage-aware views with information parity (every view encodes the same attribute set, differing only in where features attach) over 30 open-source IP cores (up to 106 nodes/edges). R2G provides an end-to-end DEF-to-graph pipeline spanning synthesis, placement, and routing stages, together with loaders, unified splits, domain metrics, and reproducible baselines. By decoupling representation choice from model choice, R2G isolates a confound that prior EDA and graph-ML benchmarks leave uncontrolled. In systematic studies with GINE, GAT, and ResGatedGCN, we find: (i) view choice dominates model choice, with Test R2 varying by more than 0.3 across representations for a fixed GNN; (ii) node-centric views generalize best across both placement and routing; and (iii) decoder-head depth (3--4 layers) is the primary accuracy driver, turning divergent training into near-perfect predictions (R2>0.99). Code and datasets are available at https://github.com/ShenShan123/R2G.
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References · 19
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- 2023CktGNN: Circuit Graph Neural Network for Electronic Design Automationcited by 55
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- 2021OpenABC-D: A Large-Scale Dataset For Machine Learning Guided Integrated Circuit Synthesiscited by 30
- 2024DeepGate3: Towards Scalable Circuit Representation Learningcited by 26
7 more
- 2022CircuitNet: An Open-Source Dataset for Machine Learning Applications in Electronic Design Automation (EDA)cited by 10
- 2025ForgeEDA: A Comprehensive Multimodal Dataset for Advancing EDAcited by 8
- 2024DE-HNN: An effective neural model for Circuit Netlist representationcited by 7
- 2024OpenLS-DGF: An Adaptive Open-Source Dataset Generation Framework for Machine Learning Tasks in Logic Synthesiscited by 3
- 2023EDALearn: A Comprehensive RTL-to-Signoff EDA Benchmark for Democratized and Reproducible ML for EDA Researchcited by 2
- 2025Deep-Learning-Based Pre-Layout Parasitic Capacitance Prediction on SRAM Designscited by 2
- 2025Few-shot Learning on AMS Circuits and Its Application to Parasitic Capacitance Predictioncited by 1
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