MARVEL: Multi-Agent RTL Vulnerability Extraction using Large Language Models
On the map: LLM agents and tool use → Agent threats, guardrails and governance
Abstract (arXiv)
Hardware security verification is a challenging and time-consuming task. Design engineers may use formal verification, linting, and functional simulation tests, coupled with analysis and a deep understanding of the hardware design being inspected. Large Language Models (LLMs) have been used to assist during this task, either directly or in conjunction with existing tools. We improve the state of the art by proposing MARVEL, a multi-agent LLM framework for a unified approach to decision-making, tool use, and reasoning. MARVEL mimics the cognitive process of a designer looking for security vulnerabilities in RTL code. It consists of a supervisor agent that devises the security policy of the system-on-chips (SoCs) using its security documentation. It delegates tasks to validate the security policy to individual executor agents. Each executor agent carries out its assigned task using a particular strategy. Each executor agent may use one or more tools to identify potential security bugs in the design and send the results back to the supervisor agent for further analysis and confirmation. MARVEL includes executor agents that leverage formal tools, linters, simulation tests, LLM-based detection schemes, and static analysis-based checks. We test our approach on a known buggy SoC based on OpenTitan from the Hack@DATE competition. We find that of the 51 issues reported by MARVEL, 19 are valid security vulnerabilities, 14 are concrete warnings, and 18 are hallucinated reports.
Key facts. Cited by 5 papers in the map (data through 14 Oct 2026). Placed in Agent threats, guardrails and governance, one of 16 directions in LLM agents and tool use. Builds on 11 of its 34 references that are in the map. First posted on arXiv 17 May 2025.
Builds on
11 of 34 references.
References · 11
- 2023A Survey on Large Language Model based Autonomous Agentscited by 2,242
- 2023Automatic Prompt Optimization with "Gradient Descent" and Beam Searchcited by 653
- 2024MEIC: Re-thinking RTL Debug Automation using LLMscited by 25
- 2023LLM for SoC Security: A Paradigm Shiftcited by 22
- 2024LLM4SecHW: Leveraging Domain Specific Large Language Model for Hardware Debuggingcited by 18
- 2024Self-HWDebug: Automation of LLM Self-Instructing for Hardware Security Verificationcited by 11
- 2025Can Reasoning Models Reason about Hardware? An Agentic HLS Perspectivecited by 9
- 2023FLAG: Finding Line Anomalies (in code) with Generative AIcited by 7
- 2025LintLLM: An Open-Source Verilog Linting Framework Based on Large Language Modelscited by 7
- 2022TheHuzz: Instruction Fuzzing of Processors Using Golden-Reference Models for Finding Software-Exploitable Vulnerabilitiescited by 5
- 2024Beyond Random Inputs: A Novel ML-Based Hardware Fuzzingcited by 3
Built on by
Citing papers per year: 2025: 2; 2026: 3.
5 papers.
- 2025OASIS: A Multilingual and Multimodal Dataset for Culturally Grounded Spoken Visual QAcited by 5
- 2025Distilled Large Language Model in Confidential Computing Environment for System-on-Chip Designcited by 2
- 2026LLMs for Secure Hardware Design and Related Problems: Opportunities and Challengescited by 1
- 2026SecureRAG-RTL: A Retrieval-Augmented, Multi-Agent, Zero-Shot LLM-Driven Framework for Hardware Vulnerability Detectioncited by 0
- 2026Hardware Design and Security in the Era of Chiplets and LLMscited by 0
- 2026Hardware Design and Security in the Era of Chiplets and LLMs5 Aug 2026
- 2026LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges11 May 2026
- 2026SecureRAG-RTL: A Retrieval-Augmented, Multi-Agent, Zero-Shot LLM-Driven Framework for Hardware Vulnerability Detection5 Mar 2026
- 2025OASIS: A Multilingual and Multimodal Dataset for Culturally Grounded Spoken Visual QA7 Oct 2025
- 2025Distilled Large Language Model in Confidential Computing Environment for System-on-Chip Design22 Jul 2025
Similar, not cited
Close in wording, no citation either way
- 2025SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models
- 2025Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification
- 2025ThreatLens: LLM-guided Threat Modeling and Test Plan Generation for Hardware Security Verification
- 2025Towards LLM-based Root Cause Analysis of Hardware Design Failures
- 2025DUET: Agentic Design Understanding via Experimentation and Testing
- 2026Argus: Reorchestrating Static Analysis via a Multi-Agent Ensemble for Full-Chain Security Vulnerability Detection
- 2025SEC-bench: Automated Benchmarking of LLM Agents on Real-World Software Security Tasks
- 2026Open-Source LLM-Driven Formal Verification: A Multi-Agent Pipeline for RTL Repair