LASHED: LLMs And Static Hardware Analysis for Early Detection of RTL Bugs
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Abstract (arXiv)
While static analysis is useful in detecting early-stage hardware security bugs, its efficacy is limited because it requires information to form checks and is often unable to explain the security impact of a detected vulnerability. Large Language Models can be useful in filling these gaps by identifying relevant assets, removing false violations flagged by static analysis tools, and explaining the reported violations. LASHED combines the two approaches (LLMs and Static Analysis) to overcome each other's limitations for hardware security bug detection. We investigate our approach on four open-source SoCs for five Common Weakness Enumerations (CWEs) and present strategies for improvement with better prompt engineering. We find that 87.5% of instances flagged by our recommended scheme are plausible CWEs. In-context learning and asking the model to 'think again' improves LASHED's precision.
Key facts. Cited by 4 papers in the map (data through 14 Oct 2026). First posted on arXiv 30 Apr 2025.
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Citing papers per year: 2026: 4.
4 papers.
- 2026VeriCWEty: Embedding enabled Line-Level CWE Detection in Verilogcited by 2
- 2026LAsset: An LLM-assisted Security Asset Identification Framework for System-on-Chip (SoC) Verificationcited by 1
- 2026LLMs for Secure Hardware Design and Related Problems: Opportunities and Challengescited by 1
- 2026Hardware Design and Security in the Era of Chiplets and LLMscited by 0
- 2026Hardware Design and Security in the Era of Chiplets and LLMs5 Aug 2026
- 2026LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges11 May 2026
- 2026VeriCWEty: Embedding enabled Line-Level CWE Detection in Verilog15 Apr 2026
- 2026LAsset: An LLM-assisted Security Asset Identification Framework for System-on-Chip (SoC) Verification6 Jan 2026