mlsanityData to 7 Oct 2026

OpenABC-D: A Large-Scale Dataset For Machine Learning Guided Integrated Circuit Synthesis

arXiv 2110.11292 ↗First posted 21 Oct 2021cs.LG cs.AI cs.SYcited by 30

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Abstract (arXiv)

Logic synthesis is a challenging and widely-researched combinatorial optimization problem during integrated circuit (IC) design. It transforms a high-level description of hardware in a programming language like Verilog into an optimized digital circuit netlist, a network of interconnected Boolean logic gates, that implements the function. Spurred by the success of ML in solving combinatorial and graph problems in other domains, there is growing interest in the design of ML-guided logic synthesis tools. Yet, there are no standard datasets or prototypical learning tasks defined for this problem domain. Here, we describe OpenABC-D,a large-scale, labeled dataset produced by synthesizing open source designs with a leading open-source logic synthesis tool and illustrate its use in developing, evaluating and benchmarking ML-guided logic synthesis. OpenABC-D has intermediate and final outputs in the form of 870,000 And-Inverter-Graphs (AIGs) produced from 1500 synthesis runs plus labels such as the optimized node counts, and de-lay. We define a generic learning problem on this dataset and benchmark existing solutions for it. The codes related to dataset creation and benchmark models are available athttps://github.com/NYU-MLDA/OpenABC.git. The dataset generated is available athttps://archive.nyu.edu/handle/2451/63311

Key facts. Cited by 30 papers in the map (data through 7 Oct 2026). Builds on 4 of its 38 references that are in the map. First posted on arXiv 21 Oct 2021.

Builds on

4 of 38 references.

References · 4

  1. 2018GLUE: A Multi-Task Benchmark and Analysis Platform for Natural Language Understandingcited by 4,854
  2. 2021Machine Learning for Electronic Design Automation: A Surveycited by 71
  3. 2019DRiLLS: Deep Reinforcement Learning for Logic Synthesiscited by 47
  4. 2018Developing Synthesis Flows Without Human Knowledgecited by 29

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Cited by year (2026 to 7 Oct)

Citing papers per year: 2022: 3; 2023: 5; 2024: 10; 2025: 7; 2026: 5.

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  1. 2023End-to-End Meta-Bayesian Optimisation with Transformer Neural Processescited by 31
  2. 2024Benchmarking End-To-End Performance of AI-Based Chip Placement Algorithmscited by 12
  3. 2025DeepGate4: Efficient and Effective Representation Learning for Circuit Design at Scalecited by 12
  4. 2025ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Modelcited by 12
  5. 2024Retrieval-Guided Reinforcement Learning for Boolean Circuit Minimizationcited by 10
  6. 2025Circuit Representation Learning with Masked Gate Modeling and Verilog-AIG Alignmentcited by 8
  7. 2023HLSDataset: Open-Source Dataset for ML-Assisted FPGA Design using High Level Synthesiscited by 4
  8. 2023INVICTUS: Optimizing Boolean Logic Circuit Synthesis via Synergistic Learning and Searchcited by 3
  9. 2024The Graph's Apprentice: Teaching an LLM Low Level Knowledge for Circuit Quality Estimationcited by 3
  10. 2024OpenLS-DGF: An Adaptive Open-Source Dataset Generation Framework for Machine Learning Tasks in Logic Synthesiscited by 3
  11. 2025VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Codecited by 3
  12. 2023EDALearn: A Comprehensive RTL-to-Signoff EDA Benchmark for Democratized and Reproducible ML for EDA Researchcited by 2
18 more
  1. 2024MTLSO: A Multi-Task Learning Approach for Logic Synthesis Optimizationcited by 2
  2. 2022Too Big to Fail? Active Few-Shot Learning Guided Logic Synthesiscited by 1
  3. 2022The prediction of the quality of results in Logic Synthesis using Transformer and Graph Neural Networkscited by 1
  4. 2022Neural Combinatorial Logic Circuit Synthesis from Input-Output Examplescited by 1
  5. 2023Towards the Imagenets of ML4EDAcited by 1
  6. 2024The Seeker's Dilemma: Realistic Formulation and Benchmarking for Hardware Trojan Detectioncited by 1
  7. 2024Logic Synthesis Optimization with Predictive Self-Supervision via Causal Transformerscited by 1
  8. 2024A Benchmark on Directed Graph Representation Learning in Hardware Designscited by 1
  9. 2024Boolean-aware Boolean Circuit Classification: A Comprehensive Study on Graph Neural Networkcited by 1
  10. 2025Functional Matching of Logic Subgraphs: Beyond Structural Isomorphismcited by 1
  11. 2025FuncGNN: Learning Functional Semantics of Logic Circuits with Graph Neural Networkscited by 1
  12. 2026CapBench: A Multi-PDK Dataset for Machine-Learning-Based Post-Layout Capacitance Extractioncited by 1
  13. 2024Hiding in Plain Sight: Reframing Hardware Trojan Benchmarking as a Hide&Seek Modificationcited by 0
  14. 2025BoolSkeleton: Boolean Network Skeletonization via Homogeneous Pattern Reductioncited by 0
  15. 2026GSR-GNN: Training Acceleration and Memory-Saving Framework of Deep GNNs on Circuit Graphcited by 0
  16. 2026R2G: A Multi-View Circuit Graph Benchmark Suite from RTL to GDSIIcited by 0
  17. 2026CircuitGate: Logic-Consistent Circuit-Level Functional Modeling for And-Inverter Graphscited by 0
  18. 2026When Algorithmic Exploration Becomes Cheap: A Case Study of Agentic Research in EDAcited by 0