LLMPirate: LLMs for Black-box Hardware IP Piracy
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Abstract (arXiv)
The rapid advancement of large language models (LLMs) has enabled the ability to effectively analyze and generate code nearly instantaneously, resulting in their widespread adoption in software development. Following this advancement, researchers and companies have begun integrating LLMs across the hardware design and verification process. However, these highly potent LLMs can also induce new attack scenarios upon security vulnerabilities across the hardware development process. One such attack vector that has not been explored is intellectual property (IP) piracy. Given that this attack can manifest as rewriting hardware designs to evade piracy detection, it is essential to thoroughly evaluate LLM capabilities in performing this task and assess the mitigation abilities of current IP piracy detection tools. Therefore, in this work, we propose LLMPirate, the first LLM-based technique able to generate pirated variations of circuit designs that successfully evade detection across multiple state-of-the-art piracy detection tools. We devise three solutions to overcome challenges related to integration of LLMs for hardware circuit designs, scalability to large circuits, and effectiveness, resulting in an end-to-end automated, efficient, and practical formulation. We perform an extensive experimental evaluation of LLMPirate using eight LLMs of varying sizes and capabilities and assess their performance in pirating various circuit designs against four state-of-the-art, widely-used piracy detection tools. Our experiments demonstrate that LLMPirate is able to consistently evade detection on 100% of tested circuits across every detection tool. Additionally, we showcase the ramifications of LLMPirate using case studies on IBEX and MOR1KX processors and a GPS module, that we successfully pirate. We envision that our work motivates and fosters the development of better IP piracy detection tools.
Key facts. Cited by 7 papers in the map (data through 14 Oct 2026). Builds on 23 of its 70 references that are in the map. First posted on arXiv 25 Nov 2024.
Builds on
23 of 70 references.
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11 more
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Built on by
Citing papers per year: 2025: 4; 2026: 3.
7 papers.
- 2025HDLCoRe: A Training-Free Framework for Mitigating Hallucinations in LLM-Generated HDLcited by 17
- 2025VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Codingcited by 11
- 2025Incident Response Planning Using a Lightweight Large Language Model with Reduced Hallucinationcited by 10
- 2025NetDeTox: Adversarial and Efficient Evasion of Hardware-Security GNNs via RL-LLM Orchestrationcited by 9
- 2026Hallucination-Resistant Security Planning with a Large Language Modelcited by 1
- 2026GUIDE: GenAI Units In Digital Design Educationcited by 1
- 2026Surveying GenAI-based Automation in Printed Circuit Board Design and Testcited by 0
- 2026Surveying GenAI-based Automation in Printed Circuit Board Design and Test10 Jun 2026
- 2026GUIDE: GenAI Units In Digital Design Education18 Mar 2026
- 2026Hallucination-Resistant Security Planning with a Large Language Model5 Feb 2026
- 2025NetDeTox: Adversarial and Efficient Evasion of Hardware-Security GNNs via RL-LLM Orchestration27 Nov 2025
- 2025Incident Response Planning Using a Lightweight Large Language Model with Reduced Hallucination7 Aug 2025
- 2025HDLCoRe: A Training-Free Framework for Mitigating Hallucinations in LLM-Generated HDL18 Mar 2025
- 2025VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Coding17 Mar 2025