ASCENT: Amplifying Power Side-Channel Resilience via Learning & Monte-Carlo Tree Search
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Abstract (arXiv)
Power side-channel (PSC) analysis is pivotal for securing cryptographic hardware. Prior art focused on securing gate-level netlists obtained as-is from chip design automation, neglecting all the complexities and potential side-effects for security arising from the design automation process. That is, automation traditionally prioritizes power, performance, and area (PPA), sidelining security. We propose a "security-first" approach, refining the logic synthesis stage to enhance the overall resilience of PSC countermeasures. We introduce ASCENT, a learning-and-search-based framework that (i) drastically reduces the time for post-design PSC evaluation and (ii) explores the security-vs-PPA design space. Thus, ASCENT enables an efficient exploration of a large number of candidate netlists, leading to an improvement in PSC resilience compared to regular PPA-optimized netlists. ASCENT is up to 120x faster than traditional PSC analysis and yields a 3.11x improvement for PSC resilience of state-of-the-art PSC countermeasures
Key facts. No citing papers in the map yet (data through 7 Oct 2026). Builds on 8 of its 35 references that are in the map. First posted on arXiv 27 Jun 2024.
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References · 8
- 2016XGBoost: A Scalable Tree Boosting Systemcited by 5,120
- 2019DRiLLS: Deep Reinforcement Learning for Logic Synthesiscited by 47
- 2024Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTScited by 42
- 2024Retrieval-Guided Reinforcement Learning for Boolean Circuit Minimizationcited by 10
- 2021SoK: Design Tools for Side-Channel-Aware Implementationscited by 3
- 2019RTL-PSC: Automated Power Side-Channel Leakage Assessment at Register-Transfer Levelcited by 2
- 2023ALMOST: Adversarial Learning to Mitigate Oracle-less ML Attacks via Synthesis Tuningcited by 2
- 2022X-Volt: Joint Tuning of Driver Strengths and Supply Voltages Against Power Side-Channel Attackscited by 1
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