FlowTune: End-to-end Automatic Logic Optimization Exploration via Domain-specific Multi-armed Bandit
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Abstract (arXiv)
Recent years have seen increasing employment of decision intelligence in electronic design automation (EDA), which aims to reduce the manual efforts and boost the design closure process in modern toolflows. However, existing approaches either require a large number of labeled data and expensive training efforts, or are limited in practical EDA toolflow integration due to computation overhead. This paper presents a generic end-to-end sequential decision making framework FlowTune for synthesis tooflow optimization, with a novel high-performance domain-specific, multi-stage multi-armed bandit (MAB) approach. This framework addresses optimization problems on Boolean optimization problems such as a) And-Inv-Graphs (# nodes), b) Conjunction Normal Form (CNF) minimization (# clauses) for Boolean Satisfiability; logic synthesis and technology mapping problems such as c) post static timing analysis (STA) delay and area optimization for standard-cell technology mapping, and d) FPGA technology mapping for 6-in LUT architectures. Moreover, we demonstrate the high extnsibility and generalizability of the proposed domain-specific MAB approach with end-to-end FPGA design flow, evaluated at post-routing stage, with two different FPGA backend tools (OpenFPGA and VPR) and two different logic synthesis representations (AIGs and MIGs). FlowTune is fully integrated with ABC [1], Yosys [2], VTR [3], LSOracle [4], OpenFPGA [5], and industrial tools, and is released publicly. The experimental results conducted on various design stages in the flow all demonstrate that our framework outperforms both hand-crafted flows [1] and ML explored flows [6], [7] in quality of results, and is orders of magnitude faster compared to ML-based approaches.
Key facts. Cited by 10 papers in the map (data through 7 Oct 2026). First posted on arXiv 15 Feb 2022.
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Citing papers per year: 2023: 3; 2024: 3; 2025: 2; 2026: 2.
10 papers.
- 2024Retrieval-Guided Reinforcement Learning for Boolean Circuit Minimizationcited by 10
- 2025MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimizationcited by 9
- 2026Autonomous Evolution of EDA Tools: Multi-Agent Self-Evolved ABCcited by 6
- 2023Verilog-to-PyG -- A Framework for Graph Learning and Augmentation on RTL Designscited by 4
- 2023INVICTUS: Optimizing Boolean Logic Circuit Synthesis via Synergistic Learning and Searchcited by 3
- 2024BoolGebra: Attributed Graph-learning for Boolean Algebraic Manipulationcited by 2
- 2024MTLSO: A Multi-Task Learning Approach for Logic Synthesis Optimizationcited by 2
- 2025e-boost: Boosted E-Graph Extraction with Adaptive Heuristics and Exact Solvingcited by 2
- 2023SEER: Super-Optimization Explorer for HLS using E-graph Rewriting with MLIRcited by 1
- 2026Rethinking Logic Optimization Operators: Theory-Derived Operator Compression via Agentic Source Analysiscited by 1
- 2026Rethinking Logic Optimization Operators: Theory-Derived Operator Compression via Agentic Source Analysis26 Jul 2026
- 2026Autonomous Evolution of EDA Tools: Multi-Agent Self-Evolved ABC16 Apr 2026
- 2025e-boost: Boosted E-Graph Extraction with Adaptive Heuristics and Exact Solving18 Aug 2025
- 2025MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization25 Jul 2025
- 2024MTLSO: A Multi-Task Learning Approach for Logic Synthesis Optimization9 Sep 2024
- 2024Retrieval-Guided Reinforcement Learning for Boolean Circuit Minimization22 Jan 2024
- 2024BoolGebra: Attributed Graph-learning for Boolean Algebraic Manipulation19 Jan 2024
- 2023Verilog-to-PyG -- A Framework for Graph Learning and Augmentation on RTL Designs9 Nov 2023
- 2023SEER: Super-Optimization Explorer for HLS using E-graph Rewriting with MLIR15 Aug 2023
- 2023INVICTUS: Optimizing Boolean Logic Circuit Synthesis via Synergistic Learning and Search22 May 2023