mlsanityData to 7 Oct 2026

Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks

arXiv 2303.08256 ↗First posted 14 Mar 2023cs.ARcited by 27

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Abstract (arXiv)

Reasoning high-level abstractions from bit-blasted Boolean networks (BNs) such as gate-level netlists can significantly benefit functional verification, logic minimization, datapath synthesis, malicious logic identification, etc. Mostly, conventional reasoning approaches leverage structural hashing and functional propagation, suffering from limited scalability and inefficient usage of modern computing power. In response, we propose a novel symbolic reasoning framework exploiting graph neural networks (GNNs) and GPU acceleration to reason high-level functional blocks from gate-level netlists, namely Gamora, which offers high reasoning performance w.r.t exact reasoning algorithms, strong scalability to BNs with over 33 million nodes, and generalization capability from simple to complex designs. To further demonstrate the capability of Gamora, we also evaluate its reasoning performance after various technology mapping options, since technology-dependent optimizations are known to make functional reasoning much more challenging. Experimental results show that (1) Gamora reaches almost 100% and over 97% reasoning accuracy for carry-save-array (CSA) and Booth-encoded multipliers, respectively, with up to six orders of magnitude speedups compared to the state-of-the-art implementation in the ABC framework; (2) Gamora maintains high reasoning accuracy (>92%) in finding functional modules after complex technology mapping, upon which we comprehensively analyze the impacts on Gamora reasoning from technology mapping.

Key facts. Cited by 27 papers in the map (data through 7 Oct 2026). First posted on arXiv 14 Mar 2023.

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Citing papers per year: 2023: 2; 2024: 6; 2025: 15; 2026: 4.

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  1. 2024DeepGate3: Towards Scalable Circuit Representation Learningcited by 26
  2. 2025DeepGate4: Efficient and Effective Representation Learning for Circuit Design at Scalecited by 12
  3. 2025NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graphcited by 9
  4. 2024Differentiable Combinatorial Scheduling at Scalecited by 6
  5. 2024DeepSeq2: Enhanced Sequential Circuit Learning with Disentangled Representationscited by 5
  6. 2023Accelerating Exact Combinatorial Optimization via RL-based Initialization -- A Case Study in Schedulingcited by 4
  7. 2023Verilog-to-PyG -- A Framework for Graph Learning and Augmentation on RTL Designscited by 4
  8. 2024OpenLS-DGF: An Adaptive Open-Source Dataset Generation Framework for Machine Learning Tasks in Logic Synthesiscited by 3
  9. 2025DeepCell: Self-Supervised Multiview Fusion for Circuit Representation Learningcited by 3
  10. 2024BoolGebra: Attributed Graph-learning for Boolean Algebraic Manipulationcited by 2
  11. 2025Graph Learning at Scale: Characterizing and Optimizing Pre-Propagation GNNscited by 2
  12. 2025e-boost: Boosted E-Graph Extraction with Adaptive Heuristics and Exact Solvingcited by 2
15 more
  1. 2024A Benchmark on Directed Graph Representation Learning in Hardware Designscited by 1
  2. 2025GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignmentcited by 1
  3. 2025Functional Matching of Logic Subgraphs: Beyond Structural Isomorphismcited by 1
  4. 2025FuncGNN: Learning Functional Semantics of Logic Circuits with Graph Neural Networkscited by 1
  5. 2025Alignment Unlocks Complementarity: A Framework for Multiview Circuit Representation Learningcited by 1
  6. 2025GROOT: Graph Edge Re-growth and Partitioning for the Verification of Large Designs in Logic Synthesiscited by 1
  7. 2026Report for NSF Workshop on AI for Electronic Design Automationcited by 1
  8. 2025Ralts: Robust Aggregation for Enhancing Graph Neural Network Resilience on Bit-flip Errorscited by 0
  9. 2025Modeling Relational Logic Circuits for And-Inverter Graph Convolutional Networkcited by 0
  10. 2025Revisit Choice Network for Synthesis and Technology Mappingcited by 0
  11. 2025TRACE: Learning to Compute on Circuit Graphscited by 0
  12. 2025ReVEAL: GNN-Guided Reverse Engineering for Formal Verification of Optimized Multiplierscited by 0
  13. 2026GauS: Differentiable Scheduling Optimization via Gaussian Reparameterizationcited by 0
  14. 2026Graph Computation Meets Circuit Algebra: A Task-Aligned Analysis of Graph Neural Networks for Electronic Design Automationcited by 0
  15. 2026Beyond Flat Netlist: Hierarchical Graph Representation Learning for Scalable Analysis of Sequential Circuitscited by 0