mlsanityData to 7 Oct 2026

DICE: Device-level Integrated Circuits Encoder with Graph Contrastive Pretraining

arXiv 2502.08949 ↗First posted 13 Feb 2025cs.LGcited by 2

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Abstract (arXiv)

Pretraining models with unsupervised graph representation learning has led to significant advancements in domains such as social network analysis, molecular design, and electronic design automation (EDA). However, prior work in EDA has mainly focused on pretraining models for digital circuits, overlooking analog and mixed-signal circuits. To bridge this gap, we introduce DICE, a Device-level Integrated Circuits Encoder, which is the first graph neural network (GNN) pretrained via self-supervised learning specifically tailored for graph-level prediction tasks in both analog and digital circuits. DICE adopts a simulation-free pretraining approach based on graph contrastive learning, leveraging two novel graph augmentation techniques. Experimental results demonstrate substantial performance improvements across three downstream tasks, highlighting the effectiveness of DICE for both analog and digital circuits. The code is available at github.com/brianlsy98/DICE.

Key facts. Cited by 2 papers in the map (data through 7 Oct 2026). Builds on 46 of its 77 references that are in the map. First posted on arXiv 13 Feb 2025.

Builds on

46 of 77 references.

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34 more
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Cited by year (2026 to 7 Oct)

Citing papers per year: 2025: 1; 2026: 1.

2 papers.

  1. 2025TopoSizing: An LLM-aided Framework of Topology-based Understanding and Sizing for AMS Circuitscited by 7
  2. 2026AMSnet-q: Unsupervised Circuit Identification and Performance Labeling for AMS Circuitscited by 0