mlsanityData to 14 Oct 2026

Verilog-to-PyG -- A Framework for Graph Learning and Augmentation on RTL Designs

arXiv 2311.05722 ↗First posted 9 Nov 2023cs.LG cs.AR cs.LOcited by 5

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Abstract (arXiv)

The complexity of modern hardware designs necessitates advanced methodologies for optimizing and analyzing modern digital systems. In recent times, machine learning (ML) methodologies have emerged as potent instruments for assessing design quality-of-results at the Register-Transfer Level (RTL) or Boolean level, aiming to expedite design exploration of advanced RTL configurations. In this presentation, we introduce an innovative open-source framework that translates RTL designs into graph representation foundations, which can be seamlessly integrated with the PyTorch Geometric graph learning platform. Furthermore, the Verilog-to-PyG (V2PYG) framework is compatible with the open-source Electronic Design Automation (EDA) toolchain OpenROAD, facilitating the collection of labeled datasets in an utterly open-source manner. Additionally, we will present novel RTL data augmentation methods (incorporated in our framework) that enable functional equivalent design augmentation for the construction of an extensive graph-based RTL design database. Lastly, we will showcase several using cases of V2PYG with detailed scripting examples. V2PYG can be found at urlhttps://yu-maryland.github.io/Verilog-to-PyG/.

Key facts. Cited by 5 papers in the map (data through 14 Oct 2026). Builds on 17 of its 43 references that are in the map. First posted on arXiv 9 Nov 2023.

Builds on

17 of 43 references.

References · 17

  1. 2019Fast Graph Representation Learning with PyTorch Geometriccited by 2,434
  2. 2020Chip Placement with Deep Reinforcement Learningcited by 83
  3. 2021A Survey of Machine Learning for Computer Architecture and Systemscited by 53
  4. 2021DeepGate: Learning Neural Representations of Logic Gatescited by 37
  5. 2023DeepGate2: Functionality-Aware Circuit Representation Learningcited by 33
  6. 2018Developing Synthesis Flows Without Human Knowledgecited by 29
  7. 2023Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networkscited by 27
  8. 2021IronMan: GNN-assisted Design Space Exploration in High-Level Synthesis via Reinforcement Learningcited by 26
  9. 2022High-Level Synthesis Performance Prediction using GNNs: Benchmarking, Modeling, and Advancingcited by 26
  10. 2022FlowTune: End-to-end Automatic Logic Optimization Exploration via Domain-specific Multi-armed Banditcited by 11
  11. 2022LOSTIN: Logic Optimization via Spatio-Temporal Information with Hybrid Graph Modelscited by 7
  12. 2022AppGNN: Approximation-Aware Functional Reverse Engineering using Graph Neural Networkscited by 7
5 more
  1. 2023RESPECT: Reinforcement Learning based Edge Scheduling on Pipelined Coral Edge TPUscited by 7
  2. 2018Standard Cell Library Design and Optimization Methodology for ASAP7 PDKcited by 6
  3. 2023Accelerating Exact Combinatorial Optimization via RL-based Initialization -- A Case Study in Schedulingcited by 4
  4. 2023INVICTUS: Optimizing Boolean Logic Circuit Synthesis via Synergistic Learning and Searchcited by 3
  5. 2023ALMOST: Adversarial Learning to Mitigate Oracle-less ML Attacks via Synthesis Tuningcited by 2

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Cited by year (2026 to 14 Oct)

Citing papers per year: 2024: 3; 2025: 1; 2026: 1.

5 papers.

  1. 2024BoolGebra: Attributed Graph-learning for Boolean Algebraic Manipulationcited by 2
  2. 2024MTLSO: A Multi-Task Learning Approach for Logic Synthesis Optimizationcited by 2
  3. 2026SafeTune: Mitigating Data Poisoning in LLM Fine-Tuning for RTL Code Generationcited by 2
  4. 2024Logic Synthesis Optimization with Predictive Self-Supervision via Causal Transformerscited by 1
  5. 2025BDD2Seq: Enabling Scalable Reversible-Circuit Synthesis via Graph-to-Sequence Learningcited by 1