mlsanityData to 7 Oct 2026

STELLAR: Structure-guided LLM Assertion Retrieval and Generation for Formal Verification

arXiv 2601.19903 ↗First posted 28 Nov 2025cs.AR cs.AIcited by 1

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Abstract (arXiv)

Formal Verification (FV) relies on high-quality SystemVerilog Assertions (SVAs), but the manual writing process is slow and error-prone. Existing LLM-based approaches either generate assertions from scratch or ignore structural patterns in hardware designs and expert-crafted assertions. This paper presents STELLAR, the first framework that guides LLM-based SVA generation with structural similarity. STELLAR represents RTL blocks as AST structural fingerprints, retrieves structurally relevant (RTL, SVA) pairs from a knowledge base, and integrates them into structure-guided prompts. Experiments show that STELLAR achieves superior syntax correctness, stylistic alignment, and functional correctness, highlighting structure-aware retrieval as a promising direction for industrial FV.

Key facts. Cited by 1 paper in the map (data through 7 Oct 2026). Builds on 10 of its 29 references that are in the map. First posted on arXiv 28 Nov 2025.

Builds on

10 of 29 references.

References · 10

  1. 2020Retrieval-Augmented Generation for Knowledge-Intensive NLP Taskscited by 9,160
  2. 2021DeepGate: Learning Neural Representations of Logic Gatescited by 37
  3. 2024AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMscited by 30
  4. 2021HW2VEC: A Graph Learning Tool for Automating Hardware Securitycited by 16
  5. 2025AssertionForge: Enhancing Formal Verification Assertion Generation with Structured Representation of Specifications and RTLcited by 13
  6. 2021AutoSVA: Democratizing Formal Verification of RTL Module Interactionscited by 12
  7. 2025Enhancing Large Language Models for Hardware Verification: A Novel SystemVerilog Assertion Datasetcited by 10
  8. 2024FVEval: Understanding Language Model Capabilities in Formal Verification of Digital Hardwarecited by 9
  9. 2024LAAG-RV: LLM Assisted Assertion Generation for RTL Design Verificationcited by 6
  10. 2025Are LLMs Ready for Practical Adoption for Assertion Generation?cited by 5

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