TreeLUT: An Efficient Alternative to Deep Neural Networks for Inference Acceleration Using Gradient Boosted Decision Trees
On the map: Efficient LLM inference and serving → Early exit and edge inference
Abstract (arXiv)
Accelerating machine learning inference has been an active research area in recent years. In this context, field-programmable gate arrays (FPGAs) have demonstrated compelling performance by providing massive parallelism in deep neural networks (DNNs). Neural networks (NNs) are computationally intensive during inference, as they require massive amounts of multiplication and addition, which makes their implementations costly. Numerous studies have recently addressed this challenge to some extent using a combination of sparsity induction, quantization, and transformation of neurons or sub-networks into lookup tables (LUTs) on FPGAs. Gradient boosted decision trees (GBDTs) are a high-accuracy alternative to DNNs in a wide range of regression and classification tasks, particularly for tabular datasets. The basic building block of GBDTs is a decision tree, which resembles the structure of binary decision diagrams. FPGA design flows are heavily optimized to implement such a structure efficiently. In addition to decision trees, GBDTs perform simple operations during inference, including comparison and addition. We present TreeLUT as an open-source tool for implementing GBDTs using an efficient quantization scheme, hardware architecture, and pipelining strategy. It primarily utilizes LUTs with no BRAMs or DSPs on FPGAs, resulting in high efficiency. We show the effectiveness of TreeLUT using multiple classification datasets, commonly used to evaluate ultra-low area and latency architectures. Using these benchmarks, we compare our implementation results with existing DNN and GBDT methods, such as DWN, PolyLUT-Add, NeuraLUT, LogicNets, FINN, hls4ml, and others. Our results show that TreeLUT significantly improves hardware utilization, latency, and throughput at competitive accuracy compared to previous works.
Key facts. Cited by 15 papers in the map (data through 7 Oct 2026). Placed in Early exit and edge inference, one of 12 directions in Efficient LLM inference and serving. Builds on 10 of its 28 references that are in the map. First posted on arXiv 2 Jan 2025.
Builds on
10 of 28 references.
References · 10
- 2016XGBoost: A Scalable Tree Boosting Systemcited by 5,120
- 2023When Do Neural Nets Outperform Boosted Trees on Tabular Data?cited by 218
- 2016FINN: A Framework for Fast, Scalable Binarized Neural Network Inferencecited by 141
- 2021hls4ml: An Open-Source Codesign Workflow to Empower Scientific Low-Power Machine Learning Devicescited by 61
- 2020LogicNets: Co-Designed Neural Networks and Circuits for Extreme-Throughput Applicationscited by 55
- 2023PolyLUT: Learning Piecewise Polynomials for Ultra-Low Latency FPGA LUT-based Inferencecited by 30
- 2020Fast inference of Boosted Decision Trees in FPGAs for particle physicscited by 26
- 2024NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functionscited by 21
- 2024PolyLUT-Add: FPGA-based LUT Inference with Wide Inputscited by 12
- 2018NullaNet: Training Deep Neural Networks for Reduced-Memory-Access Inferencecited by 3
Built on by
Citing papers per year: 2025: 7; 2026: 8.
15 papers.
Sort:
- 2025NeuraLUT-Assemble: Hardware-aware Assembling of Sub-Neural Networks for Efficient LUT Inferencecited by 14
- 2025KANEL'E: Kolmogorov-Arnold Networks for Efficient LUT-based Evaluationcited by 13
- 2025da4ml: Distributed Arithmetic for Real-time Neural Networks on FPGAscited by 8
- 2025WARP-LUTs -- Walsh-Assisted Relaxation for Probabilistic Look Up Tablescited by 6
- 2025LL-ViT: Edge Deployable Vision Transformers with Look Up Table Neuronscited by 3
- 2026WARP Logic Neural Networkscited by 2
- 2025Automating Hardware Design and Verification from Architectural Papers via a Neural-Symbolic Graph Frameworkcited by 1
- 2026Continuous-Flow Data-Rate-Aware CNN Inference on FPGAcited by 1
- 2026BitLogic: Training Framework for Gradient-Based FPGA-Native Neural Networkscited by 1
- 2026HGQ-LUT: Fast LUT-Aware Training and Efficient Architectures for DNN Inferencecited by 1
- 2025Physics-Informed Graph Neural Networks for Transverse Momentum Estimation in CMS Trigger Systemscited by 0
- 2026Enhancing LUT-based Deep Neural Networks Inference through Architecture and Connectivity Optimizationcited by 0
3 more
- 2026From Arithmetic to Logic: The Resilience of Logic and Lookup-Based Neural Networks Under Parameter Bit-Flipscited by 0
- 2026FQTree: Fine-grained Quantization and Hardware Generation of Boosted Decision Treescited by 0
- 2026DiffLUT-Net: Differentiable Training of FPGA LUT Networks with Learnable Connectivitycited by 0
- 2026DiffLUT-Net: Differentiable Training of FPGA LUT Networks with Learnable Connectivity8 Sep 2026
- 2026FQTree: Fine-grained Quantization and Hardware Generation of Boosted Decision Trees12 Aug 2026
- 2026HGQ-LUT: Fast LUT-Aware Training and Efficient Architectures for DNN Inference24 Apr 2026
- 2026From Arithmetic to Logic: The Resilience of Logic and Lookup-Based Neural Networks Under Parameter Bit-Flips24 Mar 2026
- 2026BitLogic: Training Framework for Gradient-Based FPGA-Native Neural Networks7 Feb 2026
- 2026WARP Logic Neural Networks3 Feb 2026
- 2026Continuous-Flow Data-Rate-Aware CNN Inference on FPGA16 Jan 2026
- 2026Enhancing LUT-based Deep Neural Networks Inference through Architecture and Connectivity Optimization14 Jan 2026
- 2025KANEL'E: Kolmogorov-Arnold Networks for Efficient LUT-based Evaluation14 Dec 2025
- 2025Automating Hardware Design and Verification from Architectural Papers via a Neural-Symbolic Graph Framework8 Nov 2025
- 2025LL-ViT: Edge Deployable Vision Transformers with Look Up Table Neurons2 Nov 2025
- 2025WARP-LUTs -- Walsh-Assisted Relaxation for Probabilistic Look Up Tables17 Oct 2025
3 more
- 2025Physics-Informed Graph Neural Networks for Transverse Momentum Estimation in CMS Trigger Systems25 Jul 2025
- 2025da4ml: Distributed Arithmetic for Real-time Neural Networks on FPGAs6 Jul 2025
- 2025NeuraLUT-Assemble: Hardware-aware Assembling of Sub-Neural Networks for Efficient LUT Inference1 Apr 2025
- 2025NeuraLUT-Assemble: Hardware-aware Assembling of Sub-Neural Networks for Efficient LUT Inferencecited by 14
- 2025KANEL'E: Kolmogorov-Arnold Networks for Efficient LUT-based Evaluationcited by 13
- 2025da4ml: Distributed Arithmetic for Real-time Neural Networks on FPGAscited by 8
- 2025WARP-LUTs -- Walsh-Assisted Relaxation for Probabilistic Look Up Tablescited by 6
- 2025LL-ViT: Edge Deployable Vision Transformers with Look Up Table Neuronscited by 3
- 2026WARP Logic Neural Networkscited by 2
- 2025Automating Hardware Design and Verification from Architectural Papers via a Neural-Symbolic Graph Frameworkcited by 1
- 2026Continuous-Flow Data-Rate-Aware CNN Inference on FPGAcited by 1
- 2026BitLogic: Training Framework for Gradient-Based FPGA-Native Neural Networkscited by 1
- 2026HGQ-LUT: Fast LUT-Aware Training and Efficient Architectures for DNN Inferencecited by 1
- 2025Physics-Informed Graph Neural Networks for Transverse Momentum Estimation in CMS Trigger Systemscited by 0
- 2026Enhancing LUT-based Deep Neural Networks Inference through Architecture and Connectivity Optimizationcited by 0
12 most cited of 15 All 15 (JSON)
- 2026DiffLUT-Net: Differentiable Training of FPGA LUT Networks with Learnable Connectivity8 Sep 2026
- 2026FQTree: Fine-grained Quantization and Hardware Generation of Boosted Decision Trees12 Aug 2026
- 2026HGQ-LUT: Fast LUT-Aware Training and Efficient Architectures for DNN Inference24 Apr 2026
- 2026From Arithmetic to Logic: The Resilience of Logic and Lookup-Based Neural Networks Under Parameter Bit-Flips24 Mar 2026
- 2026BitLogic: Training Framework for Gradient-Based FPGA-Native Neural Networks7 Feb 2026
- 2026WARP Logic Neural Networks3 Feb 2026
- 2026Continuous-Flow Data-Rate-Aware CNN Inference on FPGA16 Jan 2026
- 2026Enhancing LUT-based Deep Neural Networks Inference through Architecture and Connectivity Optimization14 Jan 2026
- 2025KANEL'E: Kolmogorov-Arnold Networks for Efficient LUT-based Evaluation14 Dec 2025
- 2025Automating Hardware Design and Verification from Architectural Papers via a Neural-Symbolic Graph Framework8 Nov 2025
- 2025LL-ViT: Edge Deployable Vision Transformers with Look Up Table Neurons2 Nov 2025
- 2025WARP-LUTs -- Walsh-Assisted Relaxation for Probabilistic Look Up Tables17 Oct 2025
12 newest of 15 All 15 (JSON)
Similar, not cited
Close in wording, no citation either way
- 2023GNNHLS: Evaluating Graph Neural Network Inference via High-Level Synthesis
- 2025TreeGPT: Pure TreeFFN Encoder-Decoder Architecture for Structured Reasoning Without Attention Mechanisms
- 2022DT2CAM: A Decision Tree to Content Addressable Memory Framework
- 2021A Competitive Edge: Can FPGAs Beat GPUs at DCNN Inference Acceleration in Resource-Limited Edge Computing Applications?
- 2024BUFF: Boosted Decision Tree based Ultra-Fast Flow matching
- 2024A survey on FPGA-based accelerator for ML models
- 2025Decision Trees That Remember: Gradient-Based Learning of Recurrent Decision Trees with Memory
- 2023Exploiting On-chip Heterogeneity of Versal Architecture for GNN Inference Acceleration