Flex-PE: Flexible and SIMD Multi-Precision Processing Element for AI Workloads
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Abstract (arXiv)
The rapid adaptation of data driven AI models, such as deep learning inference, training, Vision Transformers (ViTs), and other HPC applications, drives a strong need for runtime precision configurable different non linear activation functions (AF) hardware support. Existing solutions support diverse precision or runtime AF reconfigurability but fail to address both simultaneously. This work proposes a flexible and SIMD multiprecision processing element (FlexPE), which supports diverse runtime configurable AFs, including sigmoid, tanh, ReLU and softmax, and MAC operation. The proposed design achieves an improved throughput of up to 16X FxP4, 8X FxP8, 4X FxP16 and 1X FxP32 in pipeline mode with 100% time multiplexed hardware. This work proposes an area efficient multiprecision iterative mode in the SIMD systolic arrays for edge AI use cases. The design delivers superior performance with up to 62X and 371X reductions in DMA reads for input feature maps and weight filters in VGG16, with an energy efficiency of 8.42 GOPS / W within the accuracy loss of 2%. The proposed architecture supports emerging 4-bit computations for DL inference while enhancing throughput in FxP8/16 modes for transformers and other HPC applications. The proposed approach enables future energy-efficient AI accelerators in edge and cloud environments.
Key facts. Cited by 15 papers in the map (data through 14 Oct 2026). Builds on 15 of its 78 references that are in the map. First posted on arXiv 16 Dec 2024.
Builds on
15 of 78 references.
References · 15
- 2019Once-for-All: Train One Network and Specialize it for Efficient Deploymentcited by 787
- 2023TPU v4: An Optically Reconfigurable Supercomputer for Machine Learning with Hardware Support for Embeddingscited by 202
- 2021Activation Functions in Deep Learning: A Comprehensive Survey and Benchmarkcited by 155
- 2024AI and Memory Wallcited by 92
- 2021Softermax: Hardware/Software Co-Design of an Efficient Softmax for Transformerscited by 54
- 2017NullHop: A Flexible Convolutional Neural Network Accelerator Based on Sparse Representations of Feature Mapscited by 39
- 2020An Efficient Hardware Accelerator for Structured Sparse Convolutional Neural Networks on FPGAscited by 16
- 2023RAMAN: A Re-configurable and Sparse tinyML Accelerator for Inference on Edgecited by 11
- 2019Ensemble of Convolutional Neural Networks Trained with Different Activation Functionscited by 9
- 2023Cheshire: A Lightweight, Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator Plug-Incited by 7
- 2021ShortcutFusion: From Tensorflow to FPGA-based accelerator with reuse-aware memory allocation for shortcut datacited by 6
- 2018Design Space Exploration of Neural Network Activation Function Circuitscited by 4
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Citing papers per year: 2025: 8; 2026: 7.
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- 2025POLARON: Precision-aware On-device Learning and Adaptive Runtime-cONfigurable AI accelerationcited by 4
- 2025ShadowNPU: System and Algorithm Co-design for NPU-Centric On-Device LLM Inferencecited by 4
- 2025XR-NPE: High-Throughput Mixed-precision SIMD Neural Processing Engine for Extended Reality Perception Workloadscited by 3
- 2025QForce-RL: Quantized FPGA-Optimized Reinforcement Learning Compute Enginecited by 2
- 2025Automating Hardware Design and Verification from Architectural Papers via a Neural-Symbolic Graph Frameworkcited by 1
- 2025FERMI-ML: A Flexible and Resource-Efficient Memory-In-Situ SRAM Macro for TinyML accelerationcited by 1
- 2026SPADE: A SIMD Posit-enabled compute engine for Accelerating DNN Efficiencycited by 1
- 2025Retrospective: A CORDIC Based Configurable Activation Function for NN Applicationscited by 0
- 2025Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translationcited by 0
- 2026SHIELD8-UAV: Sequential 8-bit Hardware Implementation of a Precision-Aware 1D-F-CNN for Low-Energy UAV Acoustic Detection and Temporal Trackingcited by 0
- 2026L-SPINE: A Low-Precision SIMD Spiking Neural Compute Engine for Resource-efficient Edge Inferencecited by 0
- 2026MATCHA: Efficient Deployment of Deep Neural Networks on Multi-Accelerator Heterogeneous Edge SoCscited by 0
3 more
- 2026EULER-ADAS: Energy-Efficient & SIMD-Unified Logarithmic-Posit Engine for Precision-Reconfigurable Approximate ADAS Accelerationcited by 0
- 2026E-ReCON: An Energy- and Resource-Efficient Precision-Configurable Sparse nvCIM Macro for Conventional and Spiking Neural Edge Inferencecited by 0
- 2026SPARX: Secure and Privacy-Aware Approximate CNN Acceleration with Edge RISC-V SoCcited by 0
- 2026SPARX: Secure and Privacy-Aware Approximate CNN Acceleration with Edge RISC-V SoC8 Jun 2026
- 2026E-ReCON: An Energy- and Resource-Efficient Precision-Configurable Sparse nvCIM Macro for Conventional and Spiking Neural Edge Inference20 May 2026
- 2026EULER-ADAS: Energy-Efficient & SIMD-Unified Logarithmic-Posit Engine for Precision-Reconfigurable Approximate ADAS Acceleration7 May 2026
- 2026MATCHA: Efficient Deployment of Deep Neural Networks on Multi-Accelerator Heterogeneous Edge SoCs10 Apr 2026
- 2026L-SPINE: A Low-Precision SIMD Spiking Neural Compute Engine for Resource-efficient Edge Inference4 Apr 2026
- 2026SHIELD8-UAV: Sequential 8-bit Hardware Implementation of a Precision-Aware 1D-F-CNN for Low-Energy UAV Acoustic Detection and Temporal Tracking1 Mar 2026
- 2026SPADE: A SIMD Posit-enabled compute engine for Accelerating DNN Efficiency24 Jan 2026
- 2025FERMI-ML: A Flexible and Resource-Efficient Memory-In-Situ SRAM Macro for TinyML acceleration16 Nov 2025
- 2025Automating Hardware Design and Verification from Architectural Papers via a Neural-Symbolic Graph Framework8 Nov 2025
- 2025Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation12 Oct 2025
- 2025ShadowNPU: System and Algorithm Co-design for NPU-Centric On-Device LLM Inference22 Aug 2025
- 2025XR-NPE: High-Throughput Mixed-precision SIMD Neural Processing Engine for Extended Reality Perception Workloads18 Aug 2025
- 2025POLARON: Precision-aware On-device Learning and Adaptive Runtime-cONfigurable AI accelerationcited by 4
- 2025ShadowNPU: System and Algorithm Co-design for NPU-Centric On-Device LLM Inferencecited by 4
- 2025XR-NPE: High-Throughput Mixed-precision SIMD Neural Processing Engine for Extended Reality Perception Workloadscited by 3
- 2025Automating Hardware Design and Verification from Architectural Papers via a Neural-Symbolic Graph Frameworkcited by 1
- 2025FERMI-ML: A Flexible and Resource-Efficient Memory-In-Situ SRAM Macro for TinyML accelerationcited by 1
- 2026SPADE: A SIMD Posit-enabled compute engine for Accelerating DNN Efficiencycited by 1
- 2025Retrospective: A CORDIC Based Configurable Activation Function for NN Applicationscited by 0
- 2025Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translationcited by 0
- 2026SHIELD8-UAV: Sequential 8-bit Hardware Implementation of a Precision-Aware 1D-F-CNN for Low-Energy UAV Acoustic Detection and Temporal Trackingcited by 0
- 2026L-SPINE: A Low-Precision SIMD Spiking Neural Compute Engine for Resource-efficient Edge Inferencecited by 0
- 2026MATCHA: Efficient Deployment of Deep Neural Networks on Multi-Accelerator Heterogeneous Edge SoCscited by 0
- 2026EULER-ADAS: Energy-Efficient & SIMD-Unified Logarithmic-Posit Engine for Precision-Reconfigurable Approximate ADAS Accelerationcited by 0
12 most cited of 14 All 14 (JSON)
- 2026SPARX: Secure and Privacy-Aware Approximate CNN Acceleration with Edge RISC-V SoC8 Jun 2026
- 2026E-ReCON: An Energy- and Resource-Efficient Precision-Configurable Sparse nvCIM Macro for Conventional and Spiking Neural Edge Inference20 May 2026
- 2026EULER-ADAS: Energy-Efficient & SIMD-Unified Logarithmic-Posit Engine for Precision-Reconfigurable Approximate ADAS Acceleration7 May 2026
- 2026MATCHA: Efficient Deployment of Deep Neural Networks on Multi-Accelerator Heterogeneous Edge SoCs10 Apr 2026
- 2026L-SPINE: A Low-Precision SIMD Spiking Neural Compute Engine for Resource-efficient Edge Inference4 Apr 2026
- 2026SHIELD8-UAV: Sequential 8-bit Hardware Implementation of a Precision-Aware 1D-F-CNN for Low-Energy UAV Acoustic Detection and Temporal Tracking1 Mar 2026
- 2026SPADE: A SIMD Posit-enabled compute engine for Accelerating DNN Efficiency24 Jan 2026
- 2025FERMI-ML: A Flexible and Resource-Efficient Memory-In-Situ SRAM Macro for TinyML acceleration16 Nov 2025
- 2025Automating Hardware Design and Verification from Architectural Papers via a Neural-Symbolic Graph Framework8 Nov 2025
- 2025Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation12 Oct 2025
- 2025ShadowNPU: System and Algorithm Co-design for NPU-Centric On-Device LLM Inference22 Aug 2025
- 2025XR-NPE: High-Throughput Mixed-precision SIMD Neural Processing Engine for Extended Reality Perception Workloads18 Aug 2025
12 newest of 14 All 14 (JSON)
Similar, not cited
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- 2025FlexiQ: Adaptive Mixed-Precision Quantization for Latency/Accuracy Trade-Offs in Deep Neural Networks
- 2024FlexiBit: Fully Flexible Precision Bit-parallel Accelerator Architecture for Arbitrary Mixed Precision AI
- 2025FlexiSAGA: A Flexible Systolic Array GEMM Accelerator for Sparse and Dense Processing
- 2026DHFP-PE: Dual-Precision Hybrid Floating Point Processing Element for AI Acceleration ↗
- 2024Mixed-precision Neural Networks on RISC-V Cores: ISA extensions for Multi-Pumped Soft SIMD Operations
- 2025Optimizing Neural Networks with Learnable Non-Linear Activation Functions via Lookup-Based FPGA Acceleration
- 2026FlexSpIM: An Event-Based Digital Compute-In-Memory Accelerator with Flexible Operand Resolution and Layer-Wise Hybrid Stationarity ↗
- 2026FlexPosit: Tunable Fractional Precision for LLM Inference Accelerators