ReducedLUT: Table Decomposition with "Don't Care" Conditions
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Abstract (arXiv)
Lookup tables (LUTs) are frequently used to efficiently store arrays of precomputed values for complex mathematical computations. When used in the context of neural networks, these functions exhibit a lack of recognizable patterns which presents an unusual challenge for conventional logic synthesis techniques. Several approaches are known to break down a single large lookup table into multiple smaller ones that can be recombined. Traditional methods, such as plain tabulation, piecewise linear approximation, and multipartite table methods, often yield inefficient hardware solutions when applied to LUT-based NNs. This paper introduces ReducedLUT, a novel method to reduce the footprint of the LUTs by injecting don't cares into the compression process. This additional freedom introduces more self-similarities which can be exploited using known decomposition techniques. We then demonstrate a particular application to machine learning; by replacing unobserved patterns within the training data of neural network models with don't cares, we enable greater compression with minimal model accuracy degradation. In practice, we achieve up to 1.63× reduction in Physical LUT utilization, with a test accuracy drop of no more than 0.01 accuracy points.
Key facts. Cited by 7 papers in the map (data through 14 Oct 2026). Builds on 3 of its 14 references that are in the map. First posted on arXiv 24 Dec 2024.
Builds on
3 of 14 references.
References · 3
Built on by
Citing papers per year: 2025: 3; 2026: 4.
7 papers.
- 2025NeuraLUT-Assemble: Hardware-aware Assembling of Sub-Neural Networks for Efficient LUT Inferencecited by 14
- 2025LL-ViT: Edge Deployable Vision Transformers with Look Up Table Neuronscited by 3
- 2025Automating Hardware Design and Verification from Architectural Papers via a Neural-Symbolic Graph Frameworkcited by 1
- 2026Learning Compact Boolean Networkscited by 1
- 2026HGQ-LUT: Fast LUT-Aware Training and Efficient Architectures for DNN Inferencecited by 1
- 2026From Arithmetic to Logic: The Resilience of Logic and Lookup-Based Neural Networks Under Parameter Bit-Flipscited by 0
- 2026CascadeLUT: Information-Ordered Streaming Inference for Bandwidth-Constrained FPGAscited by 0
- 2026CascadeLUT: Information-Ordered Streaming Inference for Bandwidth-Constrained FPGAs1 Aug 2026
- 2026HGQ-LUT: Fast LUT-Aware Training and Efficient Architectures for DNN Inference24 Apr 2026
- 2026From Arithmetic to Logic: The Resilience of Logic and Lookup-Based Neural Networks Under Parameter Bit-Flips24 Mar 2026
- 2026Learning Compact Boolean Networks5 Feb 2026
- 2025Automating Hardware Design and Verification from Architectural Papers via a Neural-Symbolic Graph Framework8 Nov 2025
- 2025LL-ViT: Edge Deployable Vision Transformers with Look Up Table Neurons2 Nov 2025
- 2025NeuraLUT-Assemble: Hardware-aware Assembling of Sub-Neural Networks for Efficient LUT Inference1 Apr 2025