mlsanityData to 7 Oct 2026

PolyLUT-Add: FPGA-based LUT Inference with Wide Inputs

arXiv 2406.04910 ↗First posted 7 Jun 2024cs.LG cs.AI cs.ARcited by 12

Not on the map. Why?

Abstract (arXiv)

FPGAs have distinct advantages as a technology for deploying deep neural networks (DNNs) at the edge. Lookup Table (LUT) based networks, where neurons are directly modeled using LUTs, help maximize this promise of offering ultra-low latency and high area efficiency on FPGAs. Unfortunately, LUT resource usage scales exponentially with the number of inputs to the LUT, restricting PolyLUT to small LUT sizes. This work introduces PolyLUT-Add, a technique that enhances neuron connectivity by combining A PolyLUT sub-neurons via addition to improve accuracy. Moreover, we describe a novel architecture to improve its scalability. We evaluated our implementation over the MNIST, Jet Substructure classification, and Network Intrusion Detection benchmark and found that for similar accuracy, PolyLUT-Add achieves a LUT reduction of 2.0-13.9× with a 1.2-1.6× decrease in latency.

Key facts. Cited by 12 papers in the map (data through 7 Oct 2026). Builds on 9 of its 22 references that are in the map. First posted on arXiv 7 Jun 2024.

Builds on

9 of 22 references.

References · 9

  1. 2019PyTorch: An Imperative Style, High-Performance Deep Learning Librarycited by 20,160
  2. 2016FINN: A Framework for Fast, Scalable Binarized Neural Network Inferencecited by 141
  3. 2018Fast inference of deep neural networks in FPGAs for particle physicscited by 132
  4. 2020Automatic heterogeneous quantization of deep neural networks for low-latency inference on the edge for particle detectorscited by 78
  5. 2021hls4ml: An Open-Source Codesign Workflow to Empower Scientific Low-Power Machine Learning Devicescited by 61
  6. 2020LogicNets: Co-Designed Neural Networks and Circuits for Extreme-Throughput Applicationscited by 55
  7. 2020Compressing deep neural networks on FPGAs to binary and ternary precision with HLS4MLcited by 42
  8. 2023PolyLUT: Learning Piecewise Polynomials for Ultra-Low Latency FPGA LUT-based Inferencecited by 30
  9. 2019LUTNet: Rethinking Inference in FPGA Soft Logiccited by 27

Built on by

Cited by year (2026 to 7 Oct)

Citing papers per year: 2025: 6; 2026: 6.

12 papers.

  1. 2025TreeLUT: An Efficient Alternative to Deep Neural Networks for Inference Acceleration Using Gradient Boosted Decision Treescited by 15
  2. 2025NeuraLUT-Assemble: Hardware-aware Assembling of Sub-Neural Networks for Efficient LUT Inferencecited by 14
  3. 2025KANEL'E: Kolmogorov-Arnold Networks for Efficient LUT-based Evaluationcited by 13
  4. 2025da4ml: Distributed Arithmetic for Real-time Neural Networks on FPGAscited by 8
  5. 2025SparseLUT: Sparse Connectivity Optimization for Lookup Table-based Deep Neural Networkscited by 2
  6. 2025Automating Hardware Design and Verification from Architectural Papers via a Neural-Symbolic Graph Frameworkcited by 1
  7. 2026Continuous-Flow Data-Rate-Aware CNN Inference on FPGAcited by 1
  8. 2026HGQ-LUT: Fast LUT-Aware Training and Efficient Architectures for DNN Inferencecited by 1
  9. 2026Enhancing LUT-based Deep Neural Networks Inference through Architecture and Connectivity Optimizationcited by 0
  10. 2026Data-Rate-Aware High-Speed CNN Inference on FPGAscited by 0
  11. 2026Bern2Edge: A Neurosymbolic Compiler for Edge Deployment via Bernstein Polynomial Networkscited by 0
  12. 2026DiffLUT-Net: Differentiable Training of FPGA LUT Networks with Learnable Connectivitycited by 0