ATLAS: AI-Assisted Threat-to-Assertion Learning for System-on-Chip Security Verification
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Abstract (arXiv)
This work presents ATLAS, an LLM-driven framework that bridges standardized threat modeling and property-based formal verification for System-on-Chip (SoC) security. Starting from vulnerability knowledge bases such as Common Weakness Enumeration (CWE), ATLAS identifies SoC-specific assets, maps relevant weaknesses, and generates assertion-based security properties and JasperGold scripts for verification. By combining asset-centric analysis with standardized threat model templates and multi-source SoC context, ATLAS automates the transformation from vulnerability reasoning to formal proof. Evaluated on three HACK@DAC benchmarks, ATLAS detected 39/48 CWEs and generated correct properties for 33 of those bugs, advancing automated, knowledge-driven SoC security verification toward a secure-by-design paradigm.
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References · 7
- 2018Spectre Attacks: Exploiting Speculative Executioncited by 47
- 2024Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generationcited by 11
- 2025SAGE-HLS: Syntax-Aware AST-Guided LLM for High-Level Synthesis Code Generationcited by 9
- 2025VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generationcited by 8
- 2025ThreatLens: LLM-guided Threat Modeling and Test Plan Generation for Hardware Security Verificationcited by 7
- 2023MABFuzz: Multi-Armed Bandit Algorithms for Fuzzing Processorscited by 4
- 2024Security Properties for Open-Source Hardware Designscited by 2
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