mlsanityData to 14 Oct 2026

NeuraLUT-Assemble: Hardware-aware Assembling of Sub-Neural Networks for Efficient LUT Inference

arXiv 2504.00592 ↗First posted 1 Apr 2025cs.LGcited by 14

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Abstract (arXiv)

Efficient neural networks (NNs) leveraging lookup tables (LUTs) have demonstrated significant potential for emerging AI applications, particularly when deployed on field-programmable gate arrays (FPGAs) for edge computing. These architectures promise ultra-low latency and reduced resource utilization, broadening neural network adoption in fields such as particle physics. However, existing LUT-based designs suffer from accuracy degradation due to the large fan-in required by neurons being limited by the exponential scaling of LUT resources with input width. In practice, in prior work this tension has resulted in the reliance on extremely sparse models. We present NeuraLUT-Assemble, a novel framework that addresses these limitations by combining mixed-precision techniques with the assembly of larger neurons from smaller units, thereby increasing connectivity while keeping the number of inputs of any given LUT manageable. Additionally, we introduce skip-connections across entire LUT structures to improve gradient flow. NeuraLUT-Assemble closes the accuracy gap between LUT-based methods and (fully-connected) MLP-based models, achieving competitive accuracy on tasks such as network intrusion detection, digit classification, and jet classification, demonstrating up to 8.42× reduction in the area-delay product compared to the state-of-the-art at the time of the publication.

Key facts. Cited by 14 papers in the map (data through 14 Oct 2026). Builds on 17 of its 30 references that are in the map. First posted on arXiv 1 Apr 2025.

Builds on

17 of 30 references.

References · 17

  1. 2015Deep Residual Learning for Image Recognitioncited by 52,096
  2. 2016SGDR: Stochastic Gradient Descent with Warm Restartscited by 5,045
  3. 2017Decoupled Weight Decay Regularizationcited by 1,831
  4. 2016FINN: A Framework for Fast, Scalable Binarized Neural Network Inferencecited by 150
  5. 2018Fast inference of deep neural networks in FPGAs for particle physicscited by 133
  6. 2021hls4ml: An Open-Source Codesign Workflow to Empower Scientific Low-Power Machine Learning Devicescited by 62
  7. 2020LogicNets: Co-Designed Neural Networks and Circuits for Extreme-Throughput Applicationscited by 57
  8. 2020Compressing deep neural networks on FPGAs to binary and ternary precision with HLS4MLcited by 42
  9. 2023PolyLUT: Learning Piecewise Polynomials for Ultra-Low Latency FPGA LUT-based Inferencecited by 30
  10. 2019LUTNet: Rethinking Inference in FPGA Soft Logiccited by 28
  11. 2024Differentiable Weightless Neural Networkscited by 28
  12. 2019LUTNet: Learning FPGA Configurations for Highly Efficient Neural Network Inferencecited by 23
5 more
  1. 2024NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functionscited by 21
  2. 2025TreeLUT: An Efficient Alternative to Deep Neural Networks for Inference Acceleration Using Gradient Boosted Decision Treescited by 15
  3. 2024PolyLUT-Add: FPGA-based LUT Inference with Wide Inputscited by 12
  4. 2025PolyLUT: Ultra-low Latency Polynomial Inference with Hardware-Aware Structured Pruningcited by 8
  5. 2024ReducedLUT: Table Decomposition with "Don't Care" Conditionscited by 7

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Cited by year (2026 to 14 Oct)

Citing papers per year: 2025: 3; 2026: 11.

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  1. 2025Light Differentiable Logic Gate Networkscited by 9
  2. 2025da4ml: Distributed Arithmetic for Real-time Neural Networks on FPGAscited by 8
  3. 2025LUT-LLM: Efficient Large Language Model Inference with Memory-based Computations on FPGAscited by 4
  4. 2026WARP Logic Neural Networkscited by 2
  5. 2026Continuous-Flow Data-Rate-Aware CNN Inference on FPGAcited by 1
  6. 2026Learning Compact Boolean Networkscited by 1
  7. 2026BitLogic: Training Framework for Gradient-Based FPGA-Native Neural Networkscited by 1
  8. 2026HGQ-LUT: Fast LUT-Aware Training and Efficient Architectures for DNN Inferencecited by 1
  9. 2026FPGN: Redefining Ultra-Fast Programmable Gate-based Neural Acceleration with Differentiable LUTscited by 1
  10. 2026Enhancing LUT-based Deep Neural Networks Inference through Architecture and Connectivity Optimizationcited by 0
  11. 2026From Arithmetic to Logic: The Resilience of Logic and Lookup-Based Neural Networks Under Parameter Bit-Flipscited by 0
  12. 2026CascadeLUT: Information-Ordered Streaming Inference for Bandwidth-Constrained FPGAscited by 0
2 more
  1. 2026DiffLUT-Net: Differentiable Training of FPGA LUT Networks with Learnable Connectivitycited by 0
  2. 2026Overcoming Kernel Redundancy for Scaling Logic Gate Networkscited by 0