BitLogic: Training Framework for Gradient-Based FPGA-Native Neural Networks
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Abstract (arXiv)
Gradient-based LUT- and logic-gate-based neural networks (LUTNet, LogicNets, DiffLogic, PolyLUT, NeuraLUT, WARP-LUT, DWN, LILogicNet, LightLUT) replace multiply-accumulate arithmetic with Boolean lookups. The same trained checkpoint deploys to GPU as bitwise ops on bit-packed activations, to FPGA as LUT primitives, and to ASIC as standard-cell gates, all from one code path. Yet each method ships its own training pipeline, encoder, connectivity rule, fan-in, and hardware-reporting convention. The natural practitioner question, which of these choices actually matter for accuracy and which for hardware cost, therefore has no answer in the current literature. We release BitLogic, a unified framework that factors the field into a five-axis design space (encoder, connectivity, fan-in, node parameterization, head) and instantiates every prior method under one shared training and evaluation protocol. The framework deliberately omits method-specific procedures such as calibration, pruning, and thresholding, and all evaluations are limited to two-layer feed-forward networks. Combining the per-axis winners identifies a new best-of-space configuration that outperforms every retrained prior on every (dataset, width) cell in which every compared prior fits the shared budget, across MNIST, Fashion-MNIST, CIFAR-10, and CIFAR-100. We evaluate the best-of-space model on all three backends. On MNIST, the resulting two-layer network reaches ~126,MSamples/s on FPGA, ~15× the throughput of a bit-packed GPU forward path that itself processes 64 samples per 64-bit operation, at four-to-five orders of magnitude less energy.
Key facts. Cited by 1 paper in the map (data through 7 Oct 2026). Builds on 22 of its 30 references that are in the map. First posted on arXiv 7 Feb 2026.
Builds on
22 of 30 references.
References · 22
- 2018Fast inference of deep neural networks in FPGAs for particle physicscited by 132
- 2022Deep Differentiable Logic Gate Networkscited by 67
- 2020LogicNets: Co-Designed Neural Networks and Circuits for Extreme-Throughput Applicationscited by 55
- 2024Convolutional Differentiable Logic Gate Networkscited by 37
- 2023PolyLUT: Learning Piecewise Polynomials for Ultra-Low Latency FPGA LUT-based Inferencecited by 30
- 2024Differentiable Weightless Neural Networkscited by 27
- 2019LUTNet: Learning FPGA Configurations for Highly Efficient Neural Network Inferencecited by 23
- 2024NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functionscited by 21
- 2025TreeLUT: An Efficient Alternative to Deep Neural Networks for Inference Acceleration Using Gradient Boosted Decision Treescited by 15
- 2025NeuraLUT-Assemble: Hardware-aware Assembling of Sub-Neural Networks for Efficient LUT Inferencecited by 14
- 2022Weightless Neural Networks for Efficient Edge Inferencecited by 12
- 2025Recurrent Deep Differentiable Logic Gate Networkscited by 12
10 more
- 2022Open-source FPGA-ML codesign for the MLPerf Tiny Benchmarkcited by 9
- 2025Light Differentiable Logic Gate Networkscited by 9
- 2025PolyLUT: Ultra-low Latency Polynomial Inference with Hardware-Aware Structured Pruningcited by 8
- 2024Double-Exponential Increases in Inference Energy: The Cost of the Race for Accuracycited by 6
- 2025WARP-LUTs -- Walsh-Assisted Relaxation for Probabilistic Look Up Tablescited by 6
- 2025LILogic Net: Compact Logic Gate Networks with Learnable Connectivity for Efficient Hardware Deploymentcited by 6
- 2025Scalable Interconnect Learning in Boolean Networkscited by 4
- 2025LL-ViT: Edge Deployable Vision Transformers with Look Up Table Neuronscited by 3
- 2025A Survey on LUT-based Deep Neural Networks Implemented in FPGAscited by 1
- 2025From MNIST to ImageNet: Understanding the Scalability Boundaries of Differentiable Logic Gate Networkscited by 1
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