mlsanityData to 7 Oct 2026

Light Differentiable Logic Gate Networks

arXiv 2510.03250 ↗First posted 26 Sep 2025cs.LG cs.PFcited by 9

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Abstract (arXiv)

Differentiable logic gate networks (DLGNs) exhibit extraordinary efficiency at inference while sustaining competitive accuracy. But vanishing gradients, discretization errors, and high training cost impede scaling these networks. Even with dedicated parameter initialization schemes from subsequent works, increasing depth still harms accuracy. We show that the root cause of these issues lies in the underlying parametrization of logic gate neurons themselves. To overcome this issue, we propose a reparametrization that also shrinks the parameter size logarithmically in the number of inputs per gate. For binary inputs, this already reduces the model size by 4x, speeds up the backward pass by up to 1.86x, and converges in 8.5x fewer training steps. On top of that, we show that the accuracy on CIFAR-100 remains stable and sometimes superior to the original parametrization.

Key facts. Cited by 9 papers in the map (data through 7 Oct 2026). Builds on 11 of its 26 references that are in the map. First posted on arXiv 26 Sep 2025.

Builds on

11 of 26 references.

References · 11

  1. 2015Deep Residual Learning for Image Recognitioncited by 51,809
  2. 2014Deep Learning in Neural Networks: An Overviewcited by 765
  3. 2018Learning and Generalization in Overparameterized Neural Networks, Going Beyond Two Layerscited by 340
  4. 2022Deep Differentiable Logic Gate Networkscited by 67
  5. 2020LogicNets: Co-Designed Neural Networks and Circuits for Extreme-Throughput Applicationscited by 55
  6. 2024Convolutional Differentiable Logic Gate Networkscited by 37
  7. 2023PolyLUT: Learning Piecewise Polynomials for Ultra-Low Latency FPGA LUT-based Inferencecited by 30
  8. 2024Differentiable Weightless Neural Networkscited by 27
  9. 2025NeuraLUT-Assemble: Hardware-aware Assembling of Sub-Neural Networks for Efficient LUT Inferencecited by 14
  10. 2025Recurrent Deep Differentiable Logic Gate Networkscited by 12
  11. 2025PolyLUT: Ultra-low Latency Polynomial Inference with Hardware-Aware Structured Pruningcited by 8

Built on by

Cited by year (2026 to 7 Oct)

Citing papers per year: 2026: 9.

9 papers.

  1. 2026WARP Logic Neural Networkscited by 2
  2. 2026Learning Compact Boolean Networkscited by 1
  3. 2026BitLogic: Training Framework for Gradient-Based FPGA-Native Neural Networkscited by 1
  4. 2026From Arithmetic to Logic: The Resilience of Logic and Lookup-Based Neural Networks Under Parameter Bit-Flipscited by 0
  5. 2026Fitting Multilinear Polynomials for Logic Gate Networkscited by 0
  6. 2026Differentiable Logic Gate Networks for Low-Latency EEG Classification on Edge Devicescited by 0
  7. 2026DiffLUT-Net: Differentiable Training of FPGA LUT Networks with Learnable Connectivitycited by 0
  8. 2026Task-Aware Discretization of Differentiable Logic Gate Networkscited by 0
  9. 2026Overcoming Kernel Redundancy for Scaling Logic Gate Networkscited by 0