mlsanityData to 7 Oct 2026

da4ml: Distributed Arithmetic for Real-time Neural Networks on FPGAs

arXiv 2507.04535 ↗First posted 6 Jul 2025cs.AR cs.LG hep-excited by 8

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Abstract (arXiv)

Neural networks with a latency requirement on the order of microseconds, like the ones used at the CERN Large Hadron Collider, are typically deployed on FPGAs fully unrolled and pipelined. A bottleneck for the deployment of such neural networks is area utilization, which is directly related to the required constant matrix-vector multiplication (CMVM) operations. In this work, we propose an efficient algorithm for implementing CMVM operations with distributed arithmetic on FPGAs that simultaneously optimizes for area consumption and latency. The algorithm achieves resource reduction similar to state-of-the-art algorithms while being significantly faster to compute. The proposed algorithm is open-sourced and integrated into the texttthls4ml library, a free and open-source library for running real-time neural network inference on FPGAs. We show that the proposed algorithm can reduce on-chip resources by up to a third for realistic, highly quantized neural networks while simultaneously reducing latency, enabling the implementation of previously infeasible networks.

Key facts. Cited by 8 papers in the map (data through 7 Oct 2026). Builds on 18 of its 62 references that are in the map. First posted on arXiv 6 Jul 2025.

Builds on

18 of 62 references.

References · 18

  1. 2020Automatic heterogeneous quantization of deep neural networks for low-latency inference on the edge for particle detectorscited by 78
  2. 2021hls4ml: An Open-Source Codesign Workflow to Empower Scientific Low-Power Machine Learning Devicescited by 61
  3. 2020LogicNets: Co-Designed Neural Networks and Circuits for Extreme-Throughput Applicationscited by 55
  4. 2021Fast convolutional neural networks on FPGAs with hls4mlcited by 42
  5. 2024NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functionscited by 21
  6. 2023Real-time Neural Network Inference on Extremely Weak Devices: Agile Offloading with Explainable AIcited by 17
  7. 2024StreamVC: Real-Time Low-Latency Voice Conversioncited by 15
  8. 2025TreeLUT: An Efficient Alternative to Deep Neural Networks for Inference Acceleration Using Gradient Boosted Decision Treescited by 15
  9. 2025NeuraLUT-Assemble: Hardware-aware Assembling of Sub-Neural Networks for Efficient LUT Inferencecited by 14
  10. 2021Accelerating Recurrent Neural Networks for Gravitational Wave Experimentscited by 12
  11. 2022LL-GNN: Low Latency Graph Neural Networks on FPGAs for High Energy Physicscited by 12
  12. 2024Ultrafast jet classification on FPGAs for the HL-LHCcited by 12
6 more
  1. 2024PolyLUT-Add: FPGA-based LUT Inference with Wide Inputscited by 12
  2. 2021GRIM: A General, Real-Time Deep Learning Inference Framework for Mobile Devices based on Fine-Grained Structured Weight Sparsitycited by 10
  3. 2025Fast Jet Tagging with MLP-Mixers on FPGAscited by 9
  4. 2025PolyLUT: Ultra-low Latency Polynomial Inference with Hardware-Aware Structured Pruningcited by 8
  5. 2023FPGA Resource-aware Structured Pruning for Real-Time Neural Networkscited by 7
  6. 2025MetaML-Pro: Cross-Stage Design Flow Automation for Efficient Deep Learning Accelerationcited by 4

Built on by

Cited by year (2026 to 7 Oct)

Citing papers per year: 2025: 3; 2026: 5.

8 papers.

  1. 2025KANEL'E: Kolmogorov-Arnold Networks for Efficient LUT-based Evaluationcited by 13
  2. 2025hls4ml: A Flexible, Open-Source Platform for Deep Learning Acceleration on Reconfigurable Hardwarecited by 8
  3. 2025Sub-microsecond Transformers for Jet Tagging on FPGAscited by 6
  4. 2026JetFormer: A Scalable and Efficient Transformer for Jet Tagging from Offline Analysis to FPGA Triggerscited by 3
  5. 2026HGQ-LUT: Fast LUT-Aware Training and Efficient Architectures for DNN Inferencecited by 1
  6. 2026PQuantML: A Tool for End-to-End Hardware-aware Model Compressioncited by 0
  7. 2026FQTree: Fine-grained Quantization and Hardware Generation of Boosted Decision Treescited by 0
  8. 2026DiffLUT-Net: Differentiable Training of FPGA LUT Networks with Learnable Connectivitycited by 0