mlsanityData to 7 Oct 2026

Compressing deep neural networks on FPGAs to binary and ternary precision with HLS4ML

arXiv 2003.06308 ↗First posted 11 Mar 2020cs.LG eess.SP hep-excited by 42

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Abstract (arXiv)

We present the implementation of binary and ternary neural networks in the hls4ml library, designed to automatically convert deep neural network models to digital circuits with FPGA firmware. Starting from benchmark models trained with floating point precision, we investigate different strategies to reduce the network's resource consumption by reducing the numerical precision of the network parameters to binary or ternary. We discuss the trade-off between model accuracy and resource consumption. In addition, we show how to balance between latency and accuracy by retaining full precision on a selected subset of network components. As an example, we consider two multiclass classification tasks: handwritten digit recognition with the MNIST data set and jet identification with simulated proton-proton collisions at the CERN Large Hadron Collider. The binary and ternary implementation has similar performance to the higher precision implementation while using drastically fewer FPGA resources.

Key facts. Cited by 42 papers in the map (data through 7 Oct 2026). First posted on arXiv 11 Mar 2020.

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Cited by year (2026 to 7 Oct)

Citing papers per year: 2021: 8; 2022: 7; 2023: 7; 2024: 3; 2025: 10; 2026: 7.

42 papers.

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  1. 2021A Living Review of Machine Learning for Particle Physicscited by 77
  2. 2021hls4ml: An Open-Source Codesign Workflow to Empower Scientific Low-Power Machine Learning Devicescited by 61
  3. 2021Fast convolutional neural networks on FPGAs with hls4mlcited by 42
  4. 2021Applications and Techniques for Fast Machine Learning in Sciencecited by 32
  5. 2021Ps and Qs: Quantization-aware pruning for efficient low latency neural network inferencecited by 31
  6. 2023PolyLUT: Learning Piecewise Polynomials for Ultra-Low Latency FPGA LUT-based Inferencecited by 30
  7. 2024NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functionscited by 21
  8. 2021Charged particle tracking via edge-classifying interaction networkscited by 19
  9. 2021Graph Neural Networks for Charged Particle Tracking on FPGAscited by 17
  10. 2022Ultra-low latency recurrent neural network inference on FPGAs for physics applications with hls4mlcited by 14
  11. 2025NeuraLUT-Assemble: Hardware-aware Assembling of Sub-Neural Networks for Efficient LUT Inferencecited by 14
  12. 2025KANEL'E: Kolmogorov-Arnold Networks for Efficient LUT-based Evaluationcited by 13
30 more
  1. 2022Graph Neural Networks in Particle Physics: Implementations, Innovations, and Challengescited by 12
  2. 2024PolyLUT-Add: FPGA-based LUT Inference with Wide Inputscited by 12
  3. 2022Real-time semantic segmentation on FPGAs for autonomous vehicles with hls4mlcited by 11
  4. 2022Snowmass 2021 Computational Frontier CompF03 Topical Group Report: Machine Learningcited by 10
  5. 2021Nanosecond machine learning event classification with boosted decision trees in FPGA for high energy physicscited by 9
  6. 2022Open-source FPGA-ML codesign for the MLPerf Tiny Benchmarkcited by 9
  7. 2025PolyLUT: Ultra-low Latency Polynomial Inference with Hardware-Aware Structured Pruningcited by 8
  8. 2025hls4ml: A Flexible, Open-Source Platform for Deep Learning Acceleration on Reconfigurable Hardwarecited by 8
  9. 2023FPGA Resource-aware Structured Pruning for Real-Time Neural Networkscited by 7
  10. 2025Sub-microsecond Transformers for Jet Tagging on FPGAscited by 6
  11. 2022T-RECX: Tiny-Resource Efficient Convolutional neural networks with early-eXitcited by 5
  12. 2023Fast Neural Network Inference on FPGAs for Triggering on Long-Lived Particles at Colliderscited by 5
  13. 2025AIE4ML: An End-to-End Framework for Compiling Neural Networks for the Next Generation of AMD AI Enginescited by 5
  14. 2023ATHEENA: A Toolflow for Hardware Early-Exit Network Automationcited by 3
  15. 2022Physics Community Needs, Tools, and Resources for Machine Learningcited by 2
  16. 2023Ternary Quantization: A Surveycited by 2
  17. 2025SparseLUT: Sparse Connectivity Optimization for Lookup Table-based Deep Neural Networkscited by 2
  18. 2023End-to-end codesign of Hessian-aware quantized neural networks for FPGAs and ASICscited by 1
  19. 2024Leveraging Continuously Differentiable Activation Functions for Learning in Quantized Noisy Environmentscited by 1
  20. 2025Runtime Tunable Tsetlin Machines for Edge Inference on eFPGAscited by 1
  21. 2025Efficient Split Learning LSTM Models for FPGA-based Edge IoT Devicescited by 1
  22. 2025BitHEP -- The Limits of Low-Precision ML in HEPcited by 1
  23. 2026BiKA: Kolmogorov-Arnold-Network-inspired Ultra Lightweight Neural Network Hardware Acceleratorcited by 1
  24. 2026HGQ-LUT: Fast LUT-Aware Training and Efficient Architectures for DNN Inferencecited by 1
  25. 2026Spiking Neural Network inference on FPGAs with hls4mlcited by 1
  26. 2023Trees versus Neural Networks for enhancing tau lepton real-time selection in proton-proton collisionscited by 0
  27. 2026Enhancing LUT-based Deep Neural Networks Inference through Architecture and Connectivity Optimizationcited by 0
  28. 2026PiC-BNN: A 128-kbit 65 nm Processing-in-CAM-Based End-to-End Binary Neural Network Acceleratorcited by 0
  29. 2026CascadeLUT: Information-Ordered Streaming Inference for Bandwidth-Constrained FPGAscited by 0
  30. 2026DiffLUT-Net: Differentiable Training of FPGA LUT Networks with Learnable Connectivitycited by 0