Continuous-Flow Data-Rate-Aware CNN Inference on FPGA
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Abstract (arXiv)
Among hardware accelerators for deep-learning inference, data flow implementations offer low latency and high throughput capabilities. In these architectures, each neuron is mapped to a dedicated hardware unit, making them well-suited for field-programmable gate array (FPGA) implementation. Previous unrolled implementations mostly focus on fully connected networks because of their simplicity, although it is well known that convolutional neural networks (CNNs) require fewer computations for the same accuracy. When observing the data flow in CNNs, pooling layers and convolutional layers with a stride larger than one, the number of data at their output is reduced with respect to their input. This data reduction strongly affects the data rate in a fully parallel implementation, making hardware units heavily underutilized unless it is handled properly. This work addresses this issue by analyzing the data flow of CNNs and presents a novel approach to designing data-rate-aware, continuous-flow CNN architectures. The proposed approach ensures a high hardware utilization close to 100% by interleaving low data rate signals and sharing hardware units, as well as using the right parallelization to achieve the throughput of a fully parallel implementation. The results show that a significant amount of the arithmetic logic can be saved, which allows implementing complex CNNs like MobileNet on a single FPGA with high throughput.
Key facts. Cited by 1 paper in the map (data through 7 Oct 2026). Builds on 23 of its 56 references that are in the map. First posted on arXiv 16 Jan 2026.
Builds on
23 of 56 references.
References · 23
- 2015Deep Residual Learning for Image Recognitioncited by 51,809
- 2014ImageNet Large Scale Visual Recognition Challengecited by 8,441
- 2017MobileNets: Efficient Convolutional Neural Networks for Mobile Vision Applicationscited by 3,827
- 2019Object Detection in 20 Years: A Surveycited by 528
- 2017Efficient Processing of Deep Neural Networks: A Tutorial and Surveycited by 427
- 2018HAQ: Hardware-Aware Automated Quantization with Mixed Precisioncited by 426
- 2016FINN: A Framework for Fast, Scalable Binarized Neural Network Inferencecited by 141
- 2018Fast inference of deep neural networks in FPGAs for particle physicscited by 132
- 2021hls4ml: An Open-Source Codesign Workflow to Empower Scientific Low-Power Machine Learning Devicescited by 61
- 2020LogicNets: Co-Designed Neural Networks and Circuits for Extreme-Throughput Applicationscited by 55
- 2023PolyLUT: Learning Piecewise Polynomials for Ultra-Low Latency FPGA LUT-based Inferencecited by 30
- 2019LUTNet: Rethinking Inference in FPGA Soft Logiccited by 27
11 more
- 2024Differentiable Weightless Neural Networkscited by 27
- 2024NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functionscited by 21
- 2025TreeLUT: An Efficient Alternative to Deep Neural Networks for Inference Acceleration Using Gradient Boosted Decision Treescited by 15
- 2021HAO: Hardware-aware neural Architecture Optimization for Efficient Inferencecited by 14
- 2025NeuraLUT-Assemble: Hardware-aware Assembling of Sub-Neural Networks for Efficient LUT Inferencecited by 14
- 2024PolyLUT-Add: FPGA-based LUT Inference with Wide Inputscited by 12
- 2019Unrolling Ternary Neural Networkscited by 7
- 2024LUTMUL: Exceed Conventional FPGA Roofline Limit by LUT-based Efficient Multiplication for Neural Network Inferencecited by 2
- 2024Small Logic-based Multipliers with Incomplete Sub-Multipliers for FPGAscited by 1
- 2024Multiplier Design Addressing Area-Delay Trade-offs by using DSP and Logic resources on FPGAscited by 1
- 2024Kratos: An FPGA Benchmark for Unrolled DNNs with Fine-Grained Sparsity and Mixed Precisioncited by 1
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Citing papers per year: 2026: 1.
1 paper.
- 2026Data-Rate-Aware High-Speed CNN Inference on FPGAscited by 0
- 2026Data-Rate-Aware High-Speed CNN Inference on FPGAs18 Feb 2026